11-19-2018 08:26 AM
Device is ZYNQ UltraScale+ MPSOC
I want move data from PS GEMx to PL PCIe Gen3 x4. My plan is to use GEM built in DMA to move data out to PL BRAMs and then use PL PCIe DMA to move data from PL BRAMs to PCIe interface. Based on UG1085, p1056, Fig. 35-1, the path will be GEM --> IOP Outbound --> LPD Main Switch --> M_AXI_HPM0_LPD --> PL. Will it work? Is there any other better solution?
11-22-2018 04:01 AM
Could you try with M_AXI_HPM0_FPD for PS GEM to PL section which should work?
11-26-2018 06:54 AM
Based on UG1085, p1056, fig 35-1, are you suggesting GEM --> IOP Outbound --> LPD Main Switch --> CCI Coherency And Bypass --> FPD Main Switch --> M_AXI_HPM0_FPD --> PL? it seems like a longer path than using M_AXI_HPMO_LPD?
11-30-2018 09:16 AM
PS GEM has a FIFO interface to PL. (Refer page 1002 of the GEM guide in TRM http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
I am guessing you are trying to access the GEM RX/TXFIFO to transfer the data to PL BRAM using the GEM DMA engine. In that case you should be using the GEM DMA engine as a Master on the PS AXI LPD interconnect as you had mentioned in your post with a 32-bit data access width. FPD interconnect can also be used but it would be of slightly higher latency than LPD.
We have an XAPP which you can refer for more information: https://www.xilinx.com/support/documentation/application_notes/xapp1305-ps-pl-based-ethernet-solution.pdf