08-04-2020 09:05 AM
In my project a DMA is supposed to stream data towards the DDR memory of the 64-bit ARM processor of a Xilinx ultrascale, on which a Linux is running. The relevant part of the project is shown in fig.1, where the DMA IP is not present since data are streamed to the FPGA related to this project by another FPGA through a chip2chip connection: the chip2chip master, from where the DMA comes, is connected to the S_AXI_HP1_FPD AXI slave port of the processor. The DDR is mapped from 0x0 to 0x7fffffff (2G) and the AXI data bus is 32-bit wide.
If I look at the AXI transition through an ILA it looks perfectly fine (fig.2): the words I would like to see on memory are indeed 0x0000ffffe/0x0000f7ff/0x0000100. The DMA base address is 0x30060000, as obtained by the device driver with the dma_alloc_coherent kernel function and written into the related DMA IP register with the AXI-Lite bus (going from this project to the one where the DMA is through the chip2chip IP). The BVALID signal, acknowledging a succesfull AXI write access, is also there, although not present in the picture. THe interrupt signal (also sent synchronously through the chip2chip) works as expected.
After the DMA I would expect to be able to read back these three words when I read the 0x30060000/4/8 locations. However what I get is 0x0000ffff/0x0/0x0. I also verified that the first word is indeed written somehow by the DMA itself, and is not the result of some other memory access. Also, if the DMA is addressed to a bram in the PL rather than to the processor DDR memory I can correctly read the three sent words sent in the first three locations of the memory.
Any idea on the possible cause of this behavior in the processor memory?
08-04-2020 11:38 PM
Hi @ste2108 ,
Since it would be working for PL BRAM, Can you please confirm the following?
>> Make sure you are handling Xil_DCacheFlushRange function after your DMA transaction in your code to update the data in the processor DDR.
>> Ensure the read engine should have access to the processor DDR address. Hope you have taken care of this.
08-09-2020 11:13 AM
Thanks a lot for your answer.
Concerning the read engine, I can read/write the memory with "busybox devmem". The data that I can read from the DMA base address on are consistent with those in the buffer filled by the related Linux driver (which I wrote myself on the basis of a very similar one which was tested and working).
I do not use Xilinx libraries, but in my driver there are functions that should ensure that the cache is properly flushed. Also I tried to replace the "HP" with a "HPC" slave port, which as far as I understand, should guarantee access to non-cached memory (please correct me if I am wrong) but nothing changed.
Is there a way to see what is written at which address during the DMA, on the ARM side (as shown by a previous picture the DMA seems fine in the PL)? Also, can you tell me by how many bytes is the DMA base address incremented during the DMA? I would expect this to scale automatically with the bus size (e.g. with a 64-bit size the increment would be
08-12-2020 05:32 AM
I had a similar problem where I could see the AXI DMA Core write data to a particular address in ddr memory but then I could not read that data from the cpu. My design was running on a ZynqMP under FreeRTOS.
I found that switching the processor from the A53 to the R5 made my program run correctly. I don't see how this helps you but maybe it is a clue.
08-13-2020 09:17 AM
I have a similar problem.
I have an Axi master IP writing into the PS memory. I can see in the logic analyzer that the write requests of the IP are arriving at the ZynqMP.
Nevertheless, when I try to read the data using the ARM A53, I only read zeros...
Did you solve this?
08-24-2020 12:11 PM
I have finally managed to obtain correct words in the DDR memory by increasing the size of the input MPSoC AXI port up to 128 bit and putting an AXI interconnect between the 32 bit chip2chip output and this port, see the attached picture (where I highlighted the bus from the chip2chip to the Interconnect). As a test I modified the sender so that the DMA streams a 32-bit word counter, and I can see all the words where they are supposed to be (i.e. 0x0000000 at the DMA base address, 0x00000001 at base address + 4 bytes, 0x00000002 at base address + 8 bytes and so on). However I don't quite understand why it only works this way! I would expect the system to run smoothly even with a 32- or 64-bit input bus. Also I did not know that the AXI Interconnect IP can merge input words into output words when the latter is a multiple of the former: data is now copied into the DDR 128-bit wise and somehow the Interconnect correctly merges the 32-bit words.
Anyone can shed some light on these two points (why it works only in 128-bit mode and how the AXI interconnect manages to do the job)? Thanks!