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pmaurice
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Registered: ‎10-16-2020

DMA transfer tutorial

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I am using zynq ultrascale+ xu9 on custom board.

I am tryin to operate the dma transfer tutorial :

https://www.xilinx.com/support/answers/57561.html

Since I am not using a zynq7000 , i have modified the design and in vitis when i try to run debuger on the code , the function :

u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, int Direction)

return XST_FAILURE by passing there :

if(!(XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) {
if (XAxiDma_Busy(InstancePtr,Direction)) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Engine is busy\r\n");
return XST_FAILURE;
}
}

how come engine is busy ???

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pmaurice
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1,343 Views
Registered: ‎10-16-2020

I am using AXI Direct Memory Access (7.1)

I have followed Xilinx example but it is not working. I mean, HOW SURPRISING, most of their example are way out of date and don't work.

this is the only example that I could do something with it.

Others are project that need to be upgraded for use with  Vivado 2020 :

https://www.xilinx.com/support/answers/58080.html

https://www.xilinx.com/support/answers/57562.html

And I have conflict with IP data fifo that has major change. I don't need theses example to work since I don't plan to use data fifo but it could be nice to have at least 1 example working....

I almost forgot about this FFT example , the script tcl don't even achieve to build the project in vivado 2020 :

https://www.xilinx.com/support/answers/58582.html

So , I am trying to make work a simple DMA transfer loopback mode to start, but ultimately I would like to use the FFT block paired with DMA block. 

I have looked at other threads to find answer and so far... I am REALLY not impress by Xilinx's employee support overall.

View solution in original post

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9 Replies
dgisselq
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Scholar
1,375 Views
Registered: ‎05-21-2015

@pmaurice ,

Which DMA engine are you using?  The S2MM is known for locking up if it receives stream data before it is configured with a destination address and length.

Dan

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pmaurice
Participant
Participant
1,344 Views
Registered: ‎10-16-2020

I am using AXI Direct Memory Access (7.1)

I have followed Xilinx example but it is not working. I mean, HOW SURPRISING, most of their example are way out of date and don't work.

this is the only example that I could do something with it.

Others are project that need to be upgraded for use with  Vivado 2020 :

https://www.xilinx.com/support/answers/58080.html

https://www.xilinx.com/support/answers/57562.html

And I have conflict with IP data fifo that has major change. I don't need theses example to work since I don't plan to use data fifo but it could be nice to have at least 1 example working....

I almost forgot about this FFT example , the script tcl don't even achieve to build the project in vivado 2020 :

https://www.xilinx.com/support/answers/58582.html

So , I am trying to make work a simple DMA transfer loopback mode to start, but ultimately I would like to use the FFT block paired with DMA block. 

I have looked at other threads to find answer and so far... I am REALLY not impress by Xilinx's employee support overall.

View solution in original post

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pmaurice
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1,288 Views
Registered: ‎10-16-2020

I barely done progress to make work the dma.

when i execute the code from vitis :

Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);

return XST_FAILURE;
}

/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}

XAxiDma_CfgInitialize return with value 9 which is a failed to reset dma.

I have no clue how to resolve this.

 

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@pmaurice ,

This is commonly caused by either the bug I mentioned earlier, or from using a broken AXI slave--such as one of the Xilinx demos.

Dan

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adem369
Contributor
Contributor
1,264 Views
Registered: ‎02-18-2019

Are you sure? I am using design which sends stream, and then configures the DMA.I have not faced such an error so far.

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dgisselq
Scholar
Scholar
1,252 Views
Registered: ‎05-21-2015

@adem369 

Sorry, you are right.  For the stream to memory (not custom AXI) core, the most common bugs that would cause it to lock up are:

  1. Providing stream data to the DMA before the DMA is configured with a burst length and destination address
  2. Not providing TLAST at the end of the burst

Dan

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pmaurice
Participant
Participant
1,189 Views
Registered: ‎10-16-2020

I am not quite sure to understand everything mentioned.

I am trying to use a simple dma transfert.

when you connect the dma block in vivado , all thoses signals are supposed to be handled by the AXI itself?

When I try to perform dma transfert in vitis , It is like if the IP block dont get initialize well or something, because it dies in the waiting reset timeout. It is like if the IP block isnt reseted or anything at the begining and start in a faulty state.

I have deployed a ILA to check MM2S and S2MM and ILA shows inactive signals even if i put trigger setup on TLAST and TREADY.

I have no clue what to do more.

why Xilinx employee don't help ?

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pmaurice
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Participant
1,185 Views
Registered: ‎10-16-2020

My block design run the validation but I believe something is wrong.

I could achieve to make work the Bram block , but the dma block dont want to cooperate at all.

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Nitin_Kumar
Contributor
Contributor
121 Views
Registered: ‎07-28-2020

i faced the similar error, XAxiDMA_cfginitialise was not able to reset. Try using xsdb instead of running appliations from SDK itself, the problem is that you need to run fsbl before your application code.

Thanks

Nitin 

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