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user@moduleus
Contributor
Contributor
1,022 Views
Registered: ‎12-05-2017

Data transfer from PL to PS MIO peripherals

Hi,

 

I am looking for the best solution (data rate) for using my MIO peripherals (such as USB and ethernet). I have a pretty-common configuration with an external ADC attached to a deserializator.

For the moment, I use an AXI DMA connected to an HP slave port and push the streaming data into DDR before sending them through ethernet or usb (thank to the PS).

 

How can I improve that?

Should I use the S_AXI_ACP? Should I put data on the OCM? And, also, what are the use of the S_AXI_GP ports? They seems to have direct access to PS peripheral but is it possible to use them for data transfer?

My target device is Zynq7000 but I'm also interested by answers for Zynq Ultrascale+ (with its HPC ports).

Thanks in advance,

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3 Replies
abhinayp
Xilinx Employee
Xilinx Employee
954 Views
Registered: ‎07-12-2018

Hi user@moduleus,

 

I understood that you are looking for the best ways for the PS-PL communication.

System performance can be analyzed, so you can select the port which suits you.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1145-sdk-system-performance.pdf#page=30&zoom=100,0,373

Best Regards
Abhinay PS
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jg_bds
Scholar
Scholar
920 Views
Registered: ‎02-01-2013

Unless you're processing the data using the PS (in which case: kiss throughput good-bye...) you shouldn't pass it through the ACP/cache. If the PS is just a stop-over on the way out of the chip, using the OCM is best. Its performance is much better than that of DDR. OCM space is quite limited, though, so you won't have room for many buffers.

Zynq Ethernet and USB controllers have DMA front-ends, which only suck data in. There's no alternative to using those DMA's--i.e., you can't shove data into the peripherals from other means. Using the General Purpose (GP) interfaces isn't going to get you better throughput than using the High Performance (HP) interfaces (their names should have given that away...). The GP ports allow PL-based entities to access control structures in the HS peripherals, but you won't be sending data over those ports.

Note: the Zynq+ allows you to directly access the Ethernet GEM's FIFO interfaces from within the PL. You can shove data into those interfaces (after pre-pending Ethernet, IP, UDP, etc. headers, of course) to achieve sustained, maximum-rate transfers.

-Joe G.

 

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vanmierlo
Mentor
Mentor
902 Views
Registered: ‎06-10-2008

I usually require large buffers and thus use DDR.

I get the best throughput using cache coherent accesses on the ACP. And then have a separate linux process pump the data to/from a TCP port. I use DMA directly into the buffers used for the TCP transfer, so I do not need to memcpy.

I guess the most optimal solution on a Zynq would be an ethernet MAC in the PL. Then I could buffer to DDR using an HP port, relieve the ARM core and make use of jumbo-packets. But it would also require two ethernet ports.

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