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Explorer
Explorer
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Registered: ‎09-26-2014

Data transfer from PL use AXI DMA


Hello. In my custom board i wont to transfer data from PL side to PS. I successfully tested dma-proxy driver in loopback mode.

Now, i  change project, create custom AXIS master and connected to S_AXIS_S2MM.  

but I do not quite understand the sequence of data transfer.

How in PL  and PS side determine the beginning of the transfer data? 

There must be a synchronization mechanism  - betwen DMA transfer request in PS, and AXIS master in PL.

BD.jpg

There is another question - I did not find an example of DMA with DDR.
I don’t know how to connect DDR to DMA correctly.

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Moderator
Moderator
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Registered: ‎01-09-2019

Re: Data transfer from PL use AXI DMA

Hello @jack1977 

From PG021, the way that a Scatter Gather DMA is initiated is via the Tail Descriptor Pointer:

image.png

Then to determine who is initiating the transfer would be based on your MM2S or S2MM CONTROL register and NEXT DESCRIPTOR register.  These are explained in more detail in PG021.

For an example that uses AXI DMA with DDR, the AR (https://www.xilinx.com/support/answers/70413.html) should give a good idea of what a block design and basic code would look like.  That AR does provide information that was separate for 2017.4 like having to adjust the High Address option (this should now be automatically set if you are using a >32 bit addressing system).

If you want to talk to PL DDR, then all you need to do from an AXI perspective would be connect a second AXI Master port on the Smartconnect at the top of your BD to the DDR's AXI input port.  The DDR IP also needs a proper external clock (read PG150 for more details), and resets, but those should be handled by Connection Automation.

Thanks,
Caleb
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