03-31-2016 08:47 AM
07-26-2016 05:35 AM
Just to drag this one further...
I have this problem as well but it seems that data2mem can fail for a good variety of reasons. In my case, I can see the error reported by data2mem as:
ERROR::26 - Illegal bit lane width in ADDRESS_SPACE 'pcie_block_sim.pcie_sim_bd_i_cpu_microblaze_0.pcie_block_sim.pcie_sim_bd_i_cpu_microblaze_0_local_memory_lmb_bram_ADDR_SPACE'. 'pcie_block_sim.pcie_sim_bd_i/cpu_microblaze_0_local_memory_lmb_bram_BUS_BLK [31:0]' is 32 bits wide. Only 256 bit widths are allowed for this device.
This is in a design for a Kintex Ultrascale that has worked in the past and has received no modification since working. The memory in question is a 32-bit addr/data BRAM on the microblaze's LMB. In the same project, I've had it appear on other memories as well, some with 256-bit interfaces. In one case, it was fixed by using a Vivado-generated wrapper around the block diagram (which I apparently should've done anyways). In another case, that didn't fix it and I still can't simulate the design because it can't generate a BMM for the whole top-level.
Does anyone know what's up or how to see the exact data2mem command that is executed? There seems to be no way to see what it actually ran...
09-12-2016 08:19 PM
09-29-2016 05:48 AM
I forgot to post a fix once I found it. Vivado 2016.2 (at least, probably earlier) seems to have a problem mapping unique names to BRAM entities in multiple block designs. If you make two block diagrams and instantiate a BRAM in each, they will have the same name locally. While hierarchically, they have different paths when the two BDs are instantiated, something in data2mem is wholly unaware of this hierarchical name and will confuse the two memories. If they have different sizes, then you have a problem.
Give your BRAM instances unique names until this gets fixed.
11-17-2016 06:07 AM
Hello! I am trying to create a bmm file.
As template data2mem, page 15, Figure 18, is used to create bmm file .
ISE Design Suite 14.7 is used.
Project Navigator=>Tools=>FPGA EDITOR=> post map, and then highlight RAM16WER . The name notation i get is different i am not sure what notation to use and where to locate it.
Below is the name i got for the memory:
comp "core0/decode0/gprf0/a/Mram_ram", site "RAMB16_X1Y10", type = RAMB16BWER (RPM grid X97Y80)
and name from data2mem pdf:
Any help would be greatly appreciated!