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tasospet
Observer
Observer
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Registered: ‎03-14-2018

Design with 2 Microblazes - xparameters.h wrong addresses

Dear Gents,

 

We have been experimenting with a design, which contains 2 microblazes (mb0, mb1) working in parallel and communicating with a custom AXI4-Lite IP core. The aforementioned custom IP core contains two AXI4-Lite slave ports, one for each microblaze.

Each microblaze is connected as a single master with a dedicated AXI4-Lite Interconnect with a unique address (i.e. 0x46000000 for microblaze0 and 0x47000000 for microblaze1).

We came across the following strange behavior; the address editor in Vivado produces the correct addresses for the AXI4-Lite slaves but the SDK file xparameters.h produces the same address for both AXI4-Lite slaves.

Although, we assign 0x46000000 for microblaze0 and 0x47000000 for microblaze1, in both xpararameters.h we notice 0x47000000 as the address for each custom core.

 

In this design, we have various AXI4-Lite slave cores (DMAs, GPIOs) connected to either mb0 or mb1. Although it happens to use the same address for slave connected to different masters (as you can observe in the file attached), we didn't face any errors regarding the addresses generated in xparameters.h files.

 

We have to mention that in the address editor under its specific microblaze our custom IP has the same name. Maybe this is causing the problem, but we cannot change this name because the two AXI4-Lite slave ports are in the same core.

Is this a known issue or an error in our design?

 

Tools: Vivado 2017.2

Board: HTG-K800

FPGA part number: xcku085-flva1517-3e

 

Best regards,

Tasos

xilinx_case.jpg
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geoffbarnes
Explorer
Explorer
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Registered: ‎09-07-2011

Not sure..  not that familiar with the tool.

 

We used 2 microblazes like this, but our custom IP was external to the block design.  The tool just saw two unique AXI lite slaves interfaces and everything worked ok.   The busses were wired manually to the IP externally.

 

Can you put them at the same address anyways?

 

There's probably some axi stuff you can add to fool it.   A 2-master, 2-slave interconnect would allow each master to see s00_axi and s01_axi in their address space.   Extra logic though.

 

Or hack the *.h ?

 

 

 

 

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