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Participant
Participant
698 Views
Registered: ‎11-09-2017

Direct through block for AXI without address space

Hi all,

I need create block for AXI interface monitoring (only one logic output will be generated). This block will be probably connected between these two block (figure below). Signals for AXI will be fully connected together: M_AXI_AWADDR <= S_AXI_AWADDR ;, etc.

axi.PNG

My questtions:

1) Why e.g. dwith_converter and protocol_converter does not have own address mapping in address editor?

2) is it possible create this block without address mapping? 

 

Thank you in advance!

 

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Moderator
Moderator
644 Views
Registered: ‎10-30-2017

Hi @kvantum.nuly ,

 

My questtions:

1) Why e.g. dwith_converter and protocol_converter does not have own address mapping in address editor?

  Ans:     Yes, The data width converter and protocol converter does not have own address mapping as they comes between master to slave. they will take care about the data and protocol between Master and slave and Master only needs slave address to send the data. 

2) is it possible create this block without address mapping? 

  Ans:     Its possible when your block is fully configured. incase if it needs to configure from your Master then it definatly needs address mapping. Please have a look at AXI performance monitor IP. 

 

Best Regards,
Srikanth
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Participant
Participant
636 Views
Registered: ‎11-09-2017

Hi @savula,

thank you for your informations. 


@savula wrote:

...

2) is it possible create this block without address mapping? 

  Ans:     Its possible when your block is fully configured. incase if it needs to configure from your Master then it definatly needs address mapping. Please have a look at AXI performance monitor IP. 


What means "fully configured" from master address point of view?

I created block for AXI monitoring, which generate debug signal for me (no driver from this block for AXI is required). Unfortunately, in address editor i see address cell for this block, how i make my block "invisible" for this editor (address mapping)?

axi_1.PNGaxi_2.PNG

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Moderator
Moderator
627 Views
Registered: ‎10-30-2017

Hi @kvantum.nuly ,

It seems your Monitor IP is not a actual monitor and it is a pass through kind of IP.  It has both slave interface and master interface. the address map showing the Slaves connected to Master interface of your IP. Could you please let me know the purpose of your Monitor IP? If you want to monitor only AXI Transactions data width converter and protocol converter, then please use AXI performance monitor to Monitor AXI transactions.

Best Regards,

Srikanth

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Participant
Participant
619 Views
Registered: ‎11-09-2017

@savula,

In some cases, e.g. if address is invalid, AXI iterface go to "freezen" state - valid signal is asserted from slave but appropriate ready signal is still in low state. 

1. detect this situation and after timeout generate appropriate flag signal (HALT) or reset - it can be solved if AXI interface in by block are set for MODE = monitor - I tried it and  seems that it works fine - but is there any different way instead of MODE = monitor?

(2.injected ready signal for automaic "recovery", if it is possible). 

 

 

 

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Moderator
Moderator
614 Views
Registered: ‎10-30-2017

Hi @kvantum.nuly ,

if you really worried about invalid address and thought of freezen state, then please use the AXI interconnect. remove the data width converter and protocol converter and palce an AXI interconnect ( AXI interconnect have data width converter and protocol conveter inside it). The AXI interconnect will have the capability to detect the invalid address and sends the error code to the master. So there is no freezen state possible using AXI interconnect.

 

Best Regards,

Srikanth

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Scholar
Scholar
580 Views
Registered: ‎05-21-2015

I've struggled with this "frozen" state myself.  Usually I my own case it has been the result of a misbehaving slave--such as one that doesn't return responses to bus requests or such.  My solution was to create a passthrough device, much like yours above, that I call a "bus fault isolator."  Key features are that, upon detecting any slave timeout or inappropriate response, the bus fault isolator returns a bus error and sets a flag so that an internal scope can detect what just happened.  Later I adjusted the core so that it would then (optionally) issue a reset to the slave.

Only after building this did I that there was already a design within Vivado to do (nearly?) the same thing.  (Oops)  Still, it was a fun project.

Dan

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