cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
623 Views
Registered: ‎06-03-2019

Disabling interrupts to execute atomic block

Jump to solution

Hello everyone,

I am currently using ZynQ 7020 for converter control.

There are multiple ISRs involved for timing and control and I wish to update some reference values in the main loop using an atomic block. Afer going through the forum and some other technical manuals(mentioned below), I have written the following lines of code in my main loop.

asm(" CPSID I");
{
v_LV[0] = V;

umin[0] = -0.9 * v_LV[0];
umax[0] = 0.9 * v_LV[0];
pmin[0] = umin[0] * v_LV[0];
pmax[0] = umax[0] * v_LV[0];

}
asm("CPSIE I");

 

I just wanted to know if this will work safely without any exceptional cases. 


http://infocenter.arm.com/help/topic/com.arm.doc.dui0473m/DUI0473M_armasm_user_guide.pdf

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Disable-all-interrupts/td-p/883923

 

Best regards,

Pramod

 

 

Tags (3)
0 Kudos
Reply
1 Solution

Accepted Solutions
Scholar
Scholar
586 Views
Registered: ‎04-13-2015

@leo_skadoosh23 

It will for regular interrupts (IRQ) but not for fast interrupts (FIQ).

Plus the 7020 is dual core and if the other core also plays with these variables you'll need a spinlock because disabling interrupts only applies to the core CPSID is executed on.

View solution in original post

4 Replies
Scholar
Scholar
587 Views
Registered: ‎04-13-2015

@leo_skadoosh23 

It will for regular interrupts (IRQ) but not for fast interrupts (FIQ).

Plus the 7020 is dual core and if the other core also plays with these variables you'll need a spinlock because disabling interrupts only applies to the core CPSID is executed on.

View solution in original post

542 Views
Registered: ‎06-03-2019

Hello @ericv,

 

Thank you for your answer. I am not worried about FIQs being executed.

Just another follow up question, how to know which core has/uses all my variables?

Cheers,

Pramod

0 Kudos
Reply
Scholar
Scholar
526 Views
Registered: ‎04-13-2015

@leo_skadoosh23 

you can get the core # using these 2 instructions:

   mrc   p15, #0, r0, c0, c0, #5  @ Read the MPIDR
   and   r0, r0, #3               @ Isolate the CORE ID bits

508 Views
Registered: ‎06-03-2019

@ericv 

 

Thank you for your help!

Best regards,

Pramod

0 Kudos
Reply