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Observer
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Registered: ‎07-22-2018

Divide by zero bit - Zynq MPSoC RPU (R5)

Hi,

I would like to enable the generate of undefined Instruction exception when divide by zero.

According to http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbhjdah.html  - This can be done by updating C1 register bit DZ (bit number 19) to '1'.

I did nott find this bit in the "XREG_CP15_CONTROL bit defines" in xreg_cortexr5.h.

Why this bit isn't show?

Thanks!

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