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Contributor
Contributor
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Registered: ‎04-19-2017

Do Zynq UltraScale+ MPSoCs support the partial reconfiguration with ICAP?

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Hello everyone,

 

I have been following Xilinx PR ( the user guide UG909) documentation for a while, and I notice some changes in the ICAP support on Zynq UltraScale+ MPSoCs.

 

For example, in the 2017.2 version and earlier, it said ICAP is not available in Zynq UltraScale+ MPSoCs (see: UG909 - 2017.2, page 111).

 

But then in the UG909 - 2017.3 and later, ICAP is supported (page 113) in those Zynq UltraScale+ MPSoCs.

 

So I am wondering whether Zynq UltraScale+ MPSoCs really support the partial configuration with ICAP.

 

And if YES, is that support available on all ES1, ES2, and production line devices? Or just some of them?

 

And any tutorial so far?

 

Kind regards,

Khoa

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-17-2008

Re: Do Zynq UltraScale+ MPSoCs support the partial reconfiguration with ICAP?

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@khoa_pham,

 

Yes, the ICAP can be used for partial bitstream delivery on Zynq MPSoC.  UG909 v2017.3 corrected earlier omissions.  Check out details on page 119 -- in order to use the ICAP (on any Zynq), you must first request permission from the PS.  This is valid for any silicon grade, but of course we would recommend production silicon.  I am not aware of a tutorial or reference for this specific detail.

 

thanks,

david.

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Xilinx Employee
Xilinx Employee
864 Views
Registered: ‎11-17-2008

Re: Do Zynq UltraScale+ MPSoCs support the partial reconfiguration with ICAP?

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@khoa_pham,

 

Yes, the ICAP can be used for partial bitstream delivery on Zynq MPSoC.  UG909 v2017.3 corrected earlier omissions.  Check out details on page 119 -- in order to use the ICAP (on any Zynq), you must first request permission from the PS.  This is valid for any silicon grade, but of course we would recommend production silicon.  I am not aware of a tutorial or reference for this specific detail.

 

thanks,

david.

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