10-28-2010 04:07 AM
I'm working on a design that uses 2 memory chips per PPC DDR2 core.
I have set the C_NUM_RANKS_MEM to 2, which generates 2 sets of CKE and CS_N.
I believe that setting the C_DDR2_ODT_WIDTH to 2, generates an ODT signal for each chip.
However for peace of mind, I just wanted to check if anyone else has done this, and that the ODT signals are 1 per chip and not some sort of 2 bit ODT bus, used to send the ODT value.
10-28-2010 12:59 PM
I don't think you want to set C_NUM_RANKS_MEM, unless you memory is really set up as a narrow/deep configuration. Its not supported for the ppc440mc_ddr2 controller anyway.
Is you configuration wide or deep? (is you total memory width wider than each component DQ width?)