05-29-2017 03:00 AM
I'm having some issues when transferring data using a the axi dma engine in a zynq ultrascale running linux. (4.6.0) using the xilinx dma driver
For some reason, when I first submit a dma transfer to the IP, it transfers the data twice, so 2 reads are made from the same buffer (and 2 write operations).
Subsequent transfers work fine, the problem seems to affect the first transfer after the bitstream is programmed.
The design is quite simple, just a dma engine connected as a loopback (axis mm2s -> axis s2m).
I've attached two ila traces from the first and second transfers made after the bitstream is programmed.
These show that in one case the data is transferred once, but in the other case it works just fine.
Note that the exact same operations are performed in both cases.
11-03-2017 03:49 AM
As long as I know the problem should be fixed in kernels more recent than the 2016.3.
Not sure about 2016.4, but 2017 should fix this.
In our case, our vendor is only supporting 2016.3 at the moment, so I backported some driver fixes from newer kernel versions into 2016.3
You should be able to apply the attached patch to the kernel sources in the 2016.3 release.
I have only tested scatter-gather mode. Not sure if simple mode should also work.
Hope this helps :)
11-07-2017 01:16 AM
@afilgueras thank you! I switched to the 2017.2 version and it works! thank you also for the patch: I have integrated on the petalinux build but then I have a problem with the booting. BTW, we'll use the 2017.2