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Adventurer
Adventurer
8,863 Views
Registered: ‎03-31-2014

Doubts regarding AXI PCIE

I have some doubts regarding PCIe root complex port design in Zynq. KIndly clarify clarify below doubts

 

My design is a PCIe root complex.

 

1. M_AXI port of AXI PCIe logicore is for transactions  PCIe EP  ------> PCIe RP; S_AXI & S_AXI_CTL are for any master controllers' that drives communication b/w PCIe RP -------> PCIe EP. Is it true?

2. If so, where should the M_AXI port to be terminated?

 

Thanks,

Asan.

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Teacher
Teacher
8,691 Views
Registered: ‎03-31-2012

1) yes.
2) where ever the received data needs to be consumed. Probably a dma controller through which data is written into the DDR so that PS can read & process it.
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Adventurer
Adventurer
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Registered: ‎03-31-2014

@muzaffer

 

Thanks for the response.

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Teacher
Teacher
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Registered: ‎03-31-2012

please close this topic if your question is resolved.
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Adventurer
Adventurer
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Registered: ‎03-31-2014

I am trying to run a simulation using AXI PCIE, in S_AXI Custom master is sending data.

 

What needs to be configured via S_AXI_CTL port?

 

Now, axi_wready is not coming from S_AXI.

 

Thanks,

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