03-31-2016 10:00 PM
I have some doubts regarding PCIe root complex port design in Zynq. KIndly clarify clarify below doubts
My design is a PCIe root complex.
1. M_AXI port of AXI PCIe logicore is for transactions PCIe EP ------> PCIe RP; S_AXI & S_AXI_CTL are for any master controllers' that drives communication b/w PCIe RP -------> PCIe EP. Is it true?
2. If so, where should the M_AXI port to be terminated?
04-04-2016 10:59 PM
04-17-2016 11:19 PM
04-18-2016 04:55 AM
I am trying to run a simulation using AXI PCIE, in S_AXI Custom master is sending data.
What needs to be configured via S_AXI_CTL port?
Now, axi_wready is not coming from S_AXI.