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Anonymous
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EDK 13.1 ML507 - Data transfer from BRAM to xps_uartlite(RS232) usind xps_central_dma.

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Hi everyone,

I'm new to work with Xilinx EDK so I'm experiencing some difficulties on XPS and I appologize in advance if my questions sound stupid (and if I've posted in the wrong topic).

 


Here's the thing : I'm using EDK 13.1 to develop on a ML507 board with a PPC440. I'm trying to transfer data from BRAM to RS232 using the xps_central_dma. I've just used the Base System Builder without implementing any other IP and I just allow interrupt on the 2 xps_uart_lite.

Thus, both the uarts, the DMA (master and slave) and the BRAM Controler are on the same plb (with 125MHz and masters : PPC440 and DMA). I've configured both the uarts (even if I'm using only one) with a baudrate of 115200, 8 bits data, 1 bit stop and no parity.

Using some code, I managed to transfer data from BRAM to BRAM using the DMA and the uartlite seems to work perfectly either. However, when I write the TX FIFO adress on the Destination Adress of the DMA (without increment) and launch the transfer, I have a DMA Bus Error.

 


Is it more likely a software problem or an design issue ? Have anyone some idea that I can use to solve this ? Or someone that had a similar problem that they managed to solve could help me ?


Thanks,


Best regards,

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rickys
Xilinx Employee
Xilinx Employee
4,535 Views
Registered: ‎08-01-2007
xps_uartlite doesn't support burst. It needs single beat. Check C_WR_BURST_SIZE of your Central DMA configuration.

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rickys
Xilinx Employee
Xilinx Employee
4,536 Views
Registered: ‎08-01-2007
xps_uartlite doesn't support burst. It needs single beat. Check C_WR_BURST_SIZE of your Central DMA configuration.

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Anonymous
Not applicable
3,689 Views

Thanks a lot ! I didn't dheck this particular point. It works quite fine !

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