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negut
Contributor
Contributor
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Registered: ‎04-02-2019

EmptyFifo latency 1 ck cycle interrupt - spin_lock the while loop

I use UartLite in an application .Rx works fine,also Rx interrupt.

For Tx , Fifo empty interrupt can not catch.(it is active 1 clock cycle)

For send to PC from FPGA , i use XUartLite_Send but was difficult to tune the throughput rate(time between two packets which was establish with a for(k=1;k<199999;k++).The clock was set 100MHz.It seems an improper solution.

1.Can advise about  how catch send interrupt?

2.Is any timeout asociate with  "4 bytes interval" time?

 

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vanmierlo
Mentor
Mentor
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Registered: ‎06-10-2008

Are you trying to poll the interrupt line with some kind of processor? If so, which one?

Interrupts are meant to be connected to an interrupt controller or interrupt input.

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negut
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Contributor
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Registered: ‎04-02-2019

Processor is microblaze.

First let's talk about pool .Poll an interrupt in my understanding is : look for status bits of interrupt status of controller and in an task schema schedule when to check why this happen.The other way is when all jobs are pushed onto stack and processor start treating interrupt.

I use second way.it works well at every character the interrupt trigger a jump to Interrupt routine.

in an external while loop i have two spin_lock which are modified by interrupt routine (one lock  for send or the other for receive)the loop is locked until interrupt is solved.The FIFO is read in ISR and also in my undestanding if FIFO deep is 16 bytes,In receive when 1 byte enter in FIFO ,i have 15 read of empty bytes until the 16-th byte arrive at the other end of FIFO.Also for transmit will be 16 empty writes in FIFO,until FIFO will be empty.This are read and writes in FIFO (not send and receive action).These extratime should be included in throughput timing consumed.

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