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919 Views
Registered: ‎10-24-2018

Enabling DVM interface on SMMU

Hi,

I am trying to make the DVM interface work between the CPU and the SMMU so that the TLB entries on the SMMU that contain the application page table entries are being invalidated whenever an invalidation occurs by the CPU, for example when there is a free().

Unfortunately I cannot make it work, on the register reference manual UG1087 I already set and check that all the registers have been set up properly , lpd_cci, lpd_apu and Snoop_control_register_S3 to allow DVM broadcast operations, but still no luck. I also had a look on this older post which has not been resolved as yet

From the XIlinx Ultrascale+ TRM, page 364, in the figure there is clearly a DVM path between the CCI and the SMMU. In the same file, on page 79 there is an recommendation to use the DVM for freeing-up TLB entries, without specifying how.

Please, can you provide a solution or a procedure that needs to be followed so that DVMs are enabled?
My testbed includes a DMA engine deployed in PL that is initiated by the application and does DMA transfers inside the application virtual address space. The SMMU is using the application page tables. I am also using Petalinux.

Still, when there is an invalidation of a page table, or even a program termination, if I manually issue a DMA transaction, the DMA transfer will go through with the same addresses, even if these addresses should not be accessible anymore.

How can I enable the DVM interface? Am I missing something here? DVM operations seems to be propagated to the ACE port when I enable the propagation of such messages to this port.

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @ysterioustranger ,

This is the first time I've been asked about enabling this support, so please excuse any ignorant questions.

How are you setting the lpd_apu register? Are you doing this via a register write at early boot? What are you setting this register to? It should be set to 32'h00000007.

Have you modified the lpd_smmu register at all? I don't think any changes are necessary here, but want to confirm.

When I refer to early boot, this is the mechanism I am talking about:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency#ZynqUltraScaleMPSoCCacheCoherency-5.2.2RegisterWriteAtEarlyBoot

The BootROM needs to configure the lpd_apu register.

The CCI also needs to be configured as shown:

 

  • 0xFD6E1000  bits[1:0] = 0x1
  •  0xFD6E4000  bits[1:0] = 0x3

 

Regards,

Deanna

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772 Views
Registered: ‎10-24-2018

Hi Deanna,

Thanks for the answer, I am hoping that we will be able to sort this out eventually and enable this platform feature.

Regarding your questions, I am setting the lpd_apu register to 0x7 through xsdb after I load the PMU firmware. I similarly set the CCI registers with the same procedure. I read the registers when the linux boots to verify that they have been set correctly.

I am not modifying the lpd_smmu register at all.

Following your advice, I am not sure why I should set the 0xFD6E1000 bits[1:0] to 0x1, since this register enables the DVM messages between the CCI and the HPC port.

What needs to be checked next?

Thanks in advance

 

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @ysterioustranger ,

I'm working off of a bare metal example to try and figure out what needs to be set up. I making register suggestions based on that.

Just as a sanity check, could you post the xsdb script you are using to download the PMU firmware and program the APU register? I'm basically looking for your version of the script in UG1137.

https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf#page=160

It sounds like you are successful in enabling the SMMU through device tree and that the DVM messages are happening, they just aren't propagating out to TBU0. I'm assuming TBU0 is the one you care about since you mentioned configuring Snoop_control_register_S3. I'm also assuming that your PL master is connected to S_AXI_HPC0 or 1_FPD.

Is this assessment correct?

Regards,

Deanna

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Registered: ‎10-24-2018

Hi @demarco , I hope you are well, sorry for the late reply but we were experiencing a general lockdown in the UK, so there is a huge backlog. I am not using any PMU firmware other than the one used by Petalinux when I boot via JTAG.

Regarding your question yes, the accelerator is connected through the TBU0 since it is connected through the HPC0.

Let me provide the version of the .xsdb script

mwr 0xFF41a040 15    (ldp_apu, APU configuration to enable broadcasting of outer shareable transactions)

mwr 0xFD6E4000 0xc0000003 (Snoop Control register S3 to enable DVMs)

I also used to set  this register "0xFDEE1004" to "31" but I cannot find this register in the register reference manual (UG1087) nor I have physical access to the office to check my notes so I cannot recall why I set it.

What needs to be checked next?

Thanks,

Kyriakos

 

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