04-10-2018 12:08 AM
board: Avnet UltraZed-3EG IO Carrier Card
Problem is: when I generate a bitstream and I try to program FPGA in SDK, I get "bitstream is not compatible with the target revision bitstream is not compatible with the target revision".As fig.1, fig2.
I found that there is not "Parts" named "xczu3eg-sfva625-1-i-es1", when I created simple design according to this tutorial"http://zedboard.org/content/ulrazed-board-preset-files-vivado-20172" and "http://zedboard.org/content/ultrazed-board-file-20164-not-getting-detected-vivado". AS fig.3.