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Contributor
Contributor
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Registered: ‎09-05-2018

Expected AXI DMA interrupt latency

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I'm getting approximately 225 cycles of interrupt latency at a 160MHz AXI clock, from the falling edge of my TLAST signal (1 cycle) to the rising edge of the interrupt.  I am using an AXI-DMA peripheral in S2MM mode to transfer data from a custom block of IP into my DDR.  The process works, but the long interrupt latency means the FIFO fills up in the void time, which means I have to periodically reset the FIFO and this reduces the performance of my system.

1. Is this expected?

2. Can I improve this?  It seems that unless I implement a separate hardware interrupt, the delay will be large.  But I'm not sure the DMA block will be in the right state to initiate a new transaction if it is still in the process of generating an interrupt, so it may not be a good option.

Please see attached screenshot of my ILA.  (It's hard to see on the screenshot but the "0" time is set at the TLAST event falling edge, and the 225 cycle time is measured at the rising edge of the s2mm_introut signal into the PS.)

The Delay Interrupt timer value is set to zero and only IOC and Error interrupts are enabled on the PS.

ILA DMA Interrupt Delay.png
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Contributor
Contributor
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Registered: ‎09-05-2018

Re: Expected AXI DMA interrupt latency

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Turning down my burst size seems to have reduced the latency considerably.  I suspect that this latency is therefore driven by the need to complete the current burst before reading/writing the DMACR/DMASR registers.  I had a look at the IP in the schematic view and this was the only cause of this issue that I could determine as there is no deliberate timer in the interrupt process that I can otherwise see.

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Contributor
Contributor
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Registered: ‎09-05-2018

Re: Expected AXI DMA interrupt latency

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Can anyone provide any further information?

Thanks

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Highlighted
Contributor
Contributor
286 Views
Registered: ‎09-05-2018

Re: Expected AXI DMA interrupt latency

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Turning down my burst size seems to have reduced the latency considerably.  I suspect that this latency is therefore driven by the need to complete the current burst before reading/writing the DMACR/DMASR registers.  I had a look at the IP in the schematic view and this was the only cause of this issue that I could determine as there is no deliberate timer in the interrupt process that I can otherwise see.

View solution in original post

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: Expected AXI DMA interrupt latency

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@tom667,

I'm not nearly as familiar with Xilinx's S2MM controller as I am with my own.  I know that, when building my own, I set the interrupt as soon as the AXI bus write transaction is complete and the core is ready for a second transaction.  (The interrupt is also set on any stream buffer overflow.)  Until that point, the core is stuck waiting on bus responses and not (yet) ready for a next transaction.  It has to be the users responsibility, though, to size the FIFO so that it is long enough that it won't suffer from interruptions when handling this sort of thing.

Dan

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