cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
3,804 Views
Registered: ‎08-13-2014

FIFO with two AXI slaves

Hello,

 

I want to implement a fifo which has two axi slave interfaces. The reason I would like to have this implementation is so that the PCIe IP can write to the "inbound" fifo which can be read by the ARM A9 processor in Zynq. When the ARM is done processing the data, it can then write the data that it wants to communicate to the host on the "outbound" fifo for the PCIe driver to read.

 

I have gone through all the IPs in the IP catalog and it doesn't seem like there is anything for this purpose. Please propose a solution.

 

Thank you. 

0 Kudos
3 Replies
Highlighted
Explorer
Explorer
3,792 Views
Registered: ‎03-13-2014

The way to connect AXI to a FIFO is using AXI-Stream FIFO, the makes AXIS streams in and out, it is simple to connect a AXIS to a native FIFO. Not sure you will get the through put you want tho.

 

Regards

 

Dave

0 Kudos
Highlighted
Visitor
Visitor
3,787 Views
Registered: ‎08-13-2014

Hello Dave,

 

Thanks for your reply. 

 

If I am understanding what you're referring to, use a AXI Data Stream FIFO? However, that I can connect it to the PCIe for the data to flow in. How will I get the ARM to read the data from the FIFO? I was looking for a solution that will require me to drop in a fifo which has two slave ports and those two slaves can be just connected to the pcie and the ARM.

 

For your other proposed solution, I am assuming you meant that I can create an IP using the "Create AXI peripheral" options from the Tools. Is that right? I will have to implement glue logic to be able to interface the AXI data/addr along with the control signals to be able to store the data in the fifo. Is that right? Xilinx must have provided a fifo that performs read and write for two different masters. I am just not sure which IP is it. Please help! 

 

Mayank

0 Kudos
Teacher
Teacher
3,770 Views
Registered: ‎03-31-2012

It seems you are trying to save the storage between two fifo directions. This would only work if the transfer is half-duplex ie only one side is transmitting at a time. Are you sure this applies to you?

If so, I think the only way you can accomplish what you want is to create an ip block with two slave ports and have the two slave implementations take turn on writing to a regular fifo.

If you are not overly concerned about area, just use two separate fifos, one for each direction.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos