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FIR Compiler IP Block Bit Settings

Hi folks!


We are implementing a chain of FIR filters, all with the config in the attachement but different coefficients!

Sadly after the first FIR filter (if we test with a "chain" of just one filter) we are experiencing an attenuation of approximately factor 32 which would mean that something with the fixed point arithmetics is off by 5 bits. But no matter how I try, I cannot seem to find the mistake ...


Can anybody with some more experience help me spot the hopefully obvious mistake?


Thanks in advance


Screen Shot 2017-07-21 at 23.04.56.png
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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011

It is probably from bit growth in the FIR. The core calculates bit growth based on the data/coef types and also the coefficient values (or worst-case in the case of reloadable coefficients). The core guarantees no overflow via bit growth.
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