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rakeshmg
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Registered: ‎10-10-2017

FMC single ended signal routing

Hello all,

I have a zed development board, to which I have attached the xm105 Io expansion card.
I am trying to route a clock and data signal to the expansion card to be connected to an external module. I have two questions.

1) Is there anyway to configure the outputs to be 1.8v single ended?
2) When I route a user generated clock signal to the expansion card and connect the output to an oscilloscope, I see that the signal has significant overshot and understood. However, when I drive the same signal to one of the pmod pins, I the signal is much much better. Is there any special configuration required to improve the signal quality on the lpc->xm105 single ended signal?

Thanks,
Rakesh
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austin
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Registered: ‎02-27-2008

r.

 

It is called signal integrity engineering:

 

https://www.xilinx.com/products/technology/signal-integrity.html

 

Yes, you match your driver to the line/load by selecting the correct standard and IO strength:

 

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

As you are just beginning* to understand this field of knowledge (signal integrity), I suggest you do some reading, as even the use of an oscilloscope must be done in such a way that you are not misled by poor measurement practices (or wrongly setting or using the equipment).

 

(*If you were an SI engineering expert, you would already know the answers to your questions)

Austin Lesea
Principal Engineer
Xilinx San Jose
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gnarahar
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Registered: ‎07-23-2015

@rakeshmg As @austin addressed the SI part, I will try to address your 1st query


1) Is there anyway to configure the outputs to be 1.8v single ended?

Yes, you can provided the Bank you are driving the output has VCCO at 1.8V. You can use LVCMOS18 (most commonly used)

 

Having said that, I am curious on how you are driving and measuring the signals you mentioned in your 2nd question? 

- Giri
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rakeshmg
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Registered: ‎10-10-2017

@austin Thank you for the links. I will try to read up more on this signal integrity issue.

The probe that I use says that it has 13pF load and I use the 10x setting for resistance? on the probe. Is this load too much to be driven from the FPGA pin? I will also check with another probe with a lower cap value to see if the signals look better.

 

@gnarahar I have tried to drive the signal with lvcmos18 on the XM105 Card. I get an error stating that VCCO have to be the same for all the pins on the banks.

I need to change the VADJ jumper / setting to use 1.8 V instead of 2.5 V and ensure that all the ports/pins that belong to the same bank are of the same standard (either LVCMOS18 or LVCMOS25) right?

 

I am also working on the ZC706 board that has two FMC connectors. The plan is to use FMCOMMS2 board from ADI on the LPC and XM105 on the HPC connector. The FMCOMMS2 (LINK) uses LVDS 2.5V for its pins. However, I want to drive 1.8V on the XM105 pins.

 

Is this possible?

 

Thanks,

Rakesh

 

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austin
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Registered: ‎02-27-2008

The issue with the probe is the inductance as well,

 

>500 MHz measurements (required for the fast IO we have) means a special probe with less then 0.1" of leads.  Such probes require landing probe pads on the PCB to make accurate measurements.  A 6" ground lead on a 100 MHz probe is fine to see highs, lows, and signals with low frequency content, but to see rise, fall, overshoot, undershoot on our IO requires a much better setup (as described above). 

 

http://www.ni.com/tutorial/7111/en/

Austin Lesea
Principal Engineer
Xilinx San Jose
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