FPGA Verification

[noami9226@]

Hi Dears,

I have designed AXI Interconnect to connect 4 masters and one slave using AXI4 Interface. The design implemented using HDL System Verilog and Vivado tool 2018.1. The test bench of the design is working fine. 

I need your help to verify the design on the FPGA ZedBorad. What's the methodology i can follow.

If it's possible to share my design code I will do it. 

Thank You in Advance.

[drjohnsmith]

verification is a very very big subject.

It all depends by what you mean.

At one extreme,
Doe sit have to be 100 % accurate to a mathematical model that you have proven by other means

or
does it have to pass a few tests you chuck at it.

I assume you have used a test bench to help you check the code you have made ?
if not, stop now, and go back, and write some test benches. Going straight to hardware is a route for the full hardy ,

[noami9226@]

You know that there are two independent channels for write and read operations in the AXI4 Interface and each channel has handshaking signals.
My issue is: after the synthesis and implementation I have almost 150 I/O pins. How can I manage all these pins?
Thank You

[dgisselq]

noami9226@ ,

I have had the opportunity to formally verify an AXI4 crossbar (interconnect), and an AXI-lite crossbar using SymbiYosys.  I've also had the opportunity to run the formal tools on other crossbars.  It's amazing what they'll uncover.  Frankly, I'd start with the formal tools before doing anything else.  At it's most basic, you just hook up a formal property set to each of the interfaces describing how AXI works.  Slave properties to the slave interfaces, master properties to the master interfaces, etc.  The formal tool will then exhaustively search for any input combination which meets the requirements of the bus, that will break the properties required of the output combinations.

The first several clock cycles are easy.  The next 20 cost a lot of CPU power.  The rest, from 20 to infinity, take more work.  Once completed, a 4x8 AXI-lite crossbar can be proven for all eternity in less than two minutes.

Dan

[dpaul24]

noami9226@ ,

There are basically 3 ways to verify your design before implementation.

1. Functional verification in which each master writes data to the slave and then reads it back (all possible AXI4 scenarios).

2. Using an AXI4 Bus Functional Model (BFM). This method is good enough to find a lot of bugs,but not all the bugs. Problem is that free AXI4 BFM IP cores are rare to find.

3. Formal verification as mentioned by @dgisselq (Rarely done by engineers using FPGA tool-chains).

Looks like <1> has been done by you, I also recommend <2>.

I need your help to verify the design on the FPGA ZedBorad. What's the methodology i can follow.

Well AXI4 is a complete internal bus, you need not bring out the data bus to the IO pins. What you can do is to get in an UART/s and using it WRITE/READ the AXI4 registers from a terminal console. E.g. From a PC terminal console you can write 0xCAFEAFFE to a master register. Then write a bit to another control register which will start an AXI master transaction. Then again using terminal console, poll the slave register to see if 0xCAFEAFFE appears inside the slave register. Be creative in this way designing your board level tests.

Frankly speaking I guess no one performs tests like this. As AXI4 and its system are always part of the entire design, so they are implemented with the design and tested as the entire design is board tested.

[noami9226@]

Is it possible to instantiate such VIO and ILA IP cores to debug the design on the FPGA..? or the VIO doesn't support AXI transactions and I can replaced by JTAG to Master IP whom able to create the AXI4 transactions?
Thank You

[watari]

Hi noami9226@ 

Did you consider Zynq VIP (BFM) and AXI VIP to verify your design ?

If no, would you refer the following URLs ?

https://www.xilinx.com/support/documentation/ip_documentation/processing_system7_vip/v1_0/ds940-zynq-vip.pdf

https://www.xilinx.com/products/intellectual-property/axi-vip.html

Best regards,