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Visitor
Visitor
8,217 Views
Registered: ‎07-16-2014

FSL clk must be connected to where?

hey guys,

 

I'm having trouble with a FSL co-processor. It does not auto connect the FSL-clk. So I must connect it manually. but there are few choices I don't no which clock is the appropriate one for this.

 

I'm using Atlys board with Microblaze processor. My tools are xilinx EDK and SDK.

Do not go gentle into that goodnight. Rage, Rage, against the dying of the light!
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Xilinx Employee
Xilinx Employee
8,207 Views
Registered: ‎08-02-2007

hi,

 

refer to XAPP529 http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf

 

--hem

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Scholar
Scholar
8,199 Views
Registered: ‎06-14-2012

This would depend on your design requiement in terms of the clock frequency. FSL can be either be synchronous or asynchronous, the clock ports FSL_M_Clk and FSL_S_Clk are used as the master and slave clocks, respectively. If set to 0, the FSL is implemented as a synchronous FIFO. In this case, the clock port FSL_Clk is used for both the master and slave interfaces.

 

Hope this helps.

 

Regards

Sikta

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Visitor
Visitor
8,192 Views
Registered: ‎07-16-2014

Tnx for reply. It seems that I am on the right track. I use synchronous clk by connecting FSL_CLK to CLKOUT2(slowest sync clk) and leaving slave and master clocks unconnected. 

 

My problem occured when I increased RS232 BAUD RATE. I mentioned it in my other post in this forum page. Can you please give me your opinion about it. It is so ridiculous. I don't know why must rs232 baud rate have any relation with fsl processor.

Do not go gentle into that goodnight. Rage, Rage, against the dying of the light!
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Xilinx Employee
Xilinx Employee
8,127 Views
Registered: ‎08-02-2007

hi,

 

it looks that your UART issue is resolved. if you have no further questions relating to FSL clock then mark this post as solved

 

--hem

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