02-24-2015 10:37 AM
I'm having trouble with a FSL co-processor. It does not auto connect the FSL-clk. So I must connect it manually. but there are few choices I don't no which clock is the appropriate one for this.
I'm using Atlys board with Microblaze processor. My tools are xilinx EDK and SDK.
02-24-2015 04:32 PM
02-24-2015 08:51 PM
This would depend on your design requiement in terms of the clock frequency. FSL can be either be synchronous or asynchronous, the clock ports FSL_M_Clk and FSL_S_Clk are used as the master and slave clocks, respectively. If set to 0, the FSL is implemented as a synchronous FIFO. In this case, the clock port FSL_Clk is used for both the master and slave interfaces.
Hope this helps.
02-24-2015 11:53 PM
Tnx for reply. It seems that I am on the right track. I use synchronous clk by connecting FSL_CLK to CLKOUT2(slowest sync clk) and leaving slave and master clocks unconnected.
My problem occured when I increased RS232 BAUD RATE. I mentioned it in my other post in this forum page. Can you please give me your opinion about it. It is so ridiculous. I don't know why must rs232 baud rate have any relation with fsl processor.
03-02-2015 05:51 PM
it looks that your UART issue is resolved. if you have no further questions relating to FSL clock then mark this post as solved