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CollinB
Visitor
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Registered: ‎09-09-2020

Faulty Driver for Custom HLS IP Vitis 2020.1

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I am having an issue very similar to the one described in the thread here:

https://forums.xilinx.com/t5/Embedded-Development-Tools/Problem-in-Vitis-2020-1-bsp-build/td-p/1142282 

And here:

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Create-IP-AXI4-Lite/td-p/1139280

Which seems to have been resolved here:

https://www.xilinx.com/support/answers/75527.html

However, when I follow the steps for the solution, the problem still persists. Essentially, I have a custom IP core in the design that I developed using Vitis HLS. Apparently, the Vitis HLS tool does not write the make files correctly for the HLS drivers. When I followed the solution outlined in the third link above, my code is as follows:

# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.1 (64-bit)
# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
# ==============================================================
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=*.h
LIBSOURCES=*.c
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))


libs:
	echo "Compiling CalculatePhase"
	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} ${ASSEMBLY_OBJECTS}
	make clean

include: 
	${CP} $(INCLUDEFILES) $(INCLUDEDIR)

clean:
	rm -rf ${OBJECTS} ${ASSEMBLY_OBJECTS}

 

When I try to build the project, I get the following errors:

"Compiling CalculatePhase"

arm-none-eabi-ar: creating ../../../lib/libxil.a
arm-none-eabi-ar: *.o: Invalid argument
make[2]: *** [Makefile:24: libs] Error 1
make[1]: *** [Makefile:30: ps7_cortexa9_0/libsrc/CalculatePhase_v1_0/src/make.libs] Error 2
make: *** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2
make[2]: Leaving directory 'G:/EHL/Working_Directory/AXI-Core-Development/Vitis-Workspace/top_level_wrapper/zynq_fsbl/zynq_fsbl
_bsp/ps7_cortexa9_0/libsrc/CalculatePhase_v1_0/src'

make[1]: Leaving directory 'G:/EHL/Working_Directory/AXI-Core-Development/Vitis-Workspace/top_level_wrapper/zynq_fsbl/zynq_fsbl
_bsp'

 

Any ideas about why the fix mentioned above might not work and what I may do to get around it?

 

Thanks!

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CollinB
Visitor
Visitor
150 Views
Registered: ‎09-09-2020

After taking a closer look into the errors, I realized that there are two separate make files that need to be changed and I was only changing one of them. The first one was at ps7_cortexa9_0/libsrc/<custom IP name>/src/makefile and the other was in zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/<custom IP name>/src/makefile. Once I changed both according to the above directions, the project compiled just fine!

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CollinB
Visitor
Visitor
151 Views
Registered: ‎09-09-2020

After taking a closer look into the errors, I realized that there are two separate make files that need to be changed and I was only changing one of them. The first one was at ps7_cortexa9_0/libsrc/<custom IP name>/src/makefile and the other was in zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/<custom IP name>/src/makefile. Once I changed both according to the above directions, the project compiled just fine!

View solution in original post