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Participant
Participant
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Registered: ‎09-26-2016

Few basic questions regarding AXI

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Hello all,

 

I am starting to implement an embedded system based on Microblaze into Artix-7 FPGA. I have few basic questions.

 

What is the difference between implementation of AXI4 with 256 burst read/write length (AXI slave to Microblaze) and DMA implementation with the same transmission length (256)?

 

Does AXI slave need to support AXI Stream interface in case of DMA usage?

 

DMA would obviously off-load the proccesor for the transmisson (Microblaze could do something else between this time), but is this also true for the AXI4 burst tranfer? If, let say we are talking about the tranfer of 256 words.

 

Thank you in advance.

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Participant
Participant
1,632 Views
Registered: ‎09-26-2016

Hi. @demarco

 

FTDI chip (FT232H) supports parallel 8-bit sync fifo mode, which is able to transfer data with up to 40 MB/s. Their advantage is "user friendly" implementation on the FPGA side (only data bus plus few control and status lines) and also for the PC side (they have dll which is very easy to use).

 

Here is an app note for the communication interface between FPGA and FTDi chip:

http://www.ftdichip.com/Support/Documents/AppNotes/AN_130_FT2232H_Used_In_FT245%20Synchronous%20FIFO%20Mode.pdf

 

For AXI USB inmplementation, their should be an external USB PHY i guess? And the interface between AXI IP and USB is standard ULPI. Am I right? But I don't know how difficult is then implementation on the PC side.

 

I will check this XAPP anyway.

 

Thanks

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @matic,

I am guessing that your question is really about how to use the MicroBlaze with the Xilinx AXI DMA IP. 

 

In AXI, the master is the IP that initiates a transaction. The slave receives the transaction. 

 

In Xilinx systems, there are two AXI Protocols available.

1. AXI Stream: address-less transfer between master and slave

2. AXI Memory Mapped: address mapped transfers between master and slave.

 

AXI Memory Mapped is further broken down into AXI3, AXI4 and AXI-Lite.

 

AXI-Lite does not support bursting and has a limited data width. It is used for masters (like the MicroBlaze) to access configuration registers in an IP. The AXI-Lite interface in the AXI DMA IP is labeled s_axi_lite_ and provides access to the register space that sets up a DMA transfer.

 

The differences between AXI3 and AXI4 are subtle. One important difference is that AXI4 supports burst lengths up to 256 transfers while AXI3 is limited to 16.

 

The AXI DMA has up to three AXI4 master interfaces (m_axi_mm2s_, m_axi_s2mm and m_axi_sg). These interfaces connect to a slave AXI4 interface, typically on a DRAM. 

 

The AXI DMA also has up to two AXI-Stream interfaces. The s_axis_s2mm interface is a slave interface. it receives data from a streaming master like an ADC. The m_axis_mm2s interface is a master interface. It transmits data to a streaming slave like a DAC.

 

Let's say you wanted to send a buffer full of data to the DAC on the m_axis_mm2s interface. The basic steps would be:

1. MicroBlaze allocates the buffer in DRAM.

2. MicroBlaze or some other master populates the DRAM buffer with the data to send. These are burst writes.

3. MicroBlaze writes to the AXI DMA s_axi_lite_ interface to configure the mm2s registers to perform the transaction. One of the registers the MicroBlaze writes tells the AXI DMA the address in DRAM of the buffer of data to send and how many bytes to send.

4. AXI DMA uses the m_axi_mm2s_ port to read the data from DRAM at the specified address. These are burst reads.

5. AXI DMA uses the m_axis_mm2s_ port to send the data to the DAC.

6. While steps 4 and 5 are going on, the MicroBlaze can do other work. 

7. When the AXI DMA transfer completes, it can signal an interrupt to the MicroBlaze. Alternatively, the MicroBlaze can poll a register in the AXI DMA to see if the transfer has completed. 

 

If your application just needs to do memory-to-memory transfers, you may need to look at the Xilinx CDMA IP. This is the better solution if you do not have any AXI4-Stream devices in your system.

 

https://www.xilinx.com/products/intellectual-property/axi_central_dma.html

 

Regards,

 

Deanna

 

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Participant
Participant
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Registered: ‎09-26-2016

Thank you @demarco for that valuable information.

 

More precisely, I want to build a system based on MicroBlaze (as a master) which receives some commands or data tables via FTDI chip with fast 8-bit parallel sync fifo mode (USB HS on the PC side).

 

On the other side of Microblaze core, I will implement my custom logic into a custom packaged IP. These are different versions of communication interfaces (SPI, SSI, BiSS, etc) which are connected to the external device (position encoder). The whole setup will be used for a testing purposes.

 

My purpose is to keep things simple as possible, but also to achieve higher data throughput. Let say I receive some sort of a command from the FTDI chip. The whole communication interface with that chip is packaged as a custom AXI slave IP (few verilog files). The Microblaze would poll for some kind of flag, if receive buffer is full and if this is true, CPU will read data from that receive buffer. Let say this is 1 kB buffer, so the CPU should be able to read it in a single burst access (256 transactions of 4 B data path). Am I correct?

 

Then, CPU will recognise this command and trigger a logic on the other side connected to an external device. Let say, the device (encoder) sends back a lot of data which are constantly written to some sort of FIFO (which I have now implemented as a part of this logic and packaged into IP).

 

Than, the FIFO is getting full and I am checking from the CPU side how many bytes are already available. Let say, when there is 1 kB of data already in, I would like to send them to:

a) Microblaze for post-processing or,

b) directly to the FTDI output buffer (by-passing the Microblaze completely) for the transmission to the PC.

 

Now, you have a better overall image what I want to achieve. Could you now suggest if there is an appropriate place to implement a DMA (CDMA)? Maybe it would be better to implement DMA for the transmission between FIFO to Microblaze or FIFO to FTDI output buffer? Or is a simpler AXI4 burst read/write a better solution? Only using AXI4-Lite, I think the data transmission rate would not be sufficient. One thing to keep in mind is that command receiving is not time critical. But the data sending back to the PC is. This is also the reason to use FTDI sync fifo mode with USB High speed. This combination is capable to transfer around 35-40 kB/s. (which does not sound a lot if comparing to let say Ethernet, but for encoder interfaces is enough). On current version of testing system based on microcontroller we use FTDI to UART bridge with USB 1 on the PC side, which is theoretically 12 Mbit/s. And this is too slow.

 

In case that you suggest transmission over DMA, I am not sure how to define address of the FIFO as a source address for the DMA. Is maybe better if I don't implement my own FIFO as a part of custom IP and put there another Xilinx FIFO IP core, which would be written from my custom IP byte-by-byte?

 

Thanks a lot for your time and help.

 

Matic

 

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Xilinx Employee
Xilinx Employee
1,472 Views
Registered: ‎10-04-2016

Hi @matic,

For the MicroBlaze and USB side of the world, I think it would help for you to take a look at this XAPP to get an idea of what that system would look like:

 

https://www.xilinx.com/support/documentation/application_notes/xapp1263-kcu105-axi-usb2-device.pdf

 

There are a few things to note in your description that don't line up with how the XAPP system works.

1. If you are using the AXI USB IP from Xilinx, the AXI Slave Interface is for reading/writing control registers.

2. If you want to burst larger amounts of data into or out of DRAM (for example), the AXI USB includes a master AXI port and hardware to perform DMA transfers.

 

What is the interface on the FIFO for your custom IP? If you can format your data to comply with an AXI Stream interface, you could use the S2MM path on AXI DMA to transfer the custom IP data into a buffer in DRAM. From there, the MicroBlaze could perform post-processing or it could set up the USB DMA to transfer the data to your host system.

 

Regards,

 

Deanna

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Participant
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Registered: ‎09-26-2016

Hi. @demarco

 

FTDI chip (FT232H) supports parallel 8-bit sync fifo mode, which is able to transfer data with up to 40 MB/s. Their advantage is "user friendly" implementation on the FPGA side (only data bus plus few control and status lines) and also for the PC side (they have dll which is very easy to use).

 

Here is an app note for the communication interface between FPGA and FTDi chip:

http://www.ftdichip.com/Support/Documents/AppNotes/AN_130_FT2232H_Used_In_FT245%20Synchronous%20FIFO%20Mode.pdf

 

For AXI USB inmplementation, their should be an external USB PHY i guess? And the interface between AXI IP and USB is standard ULPI. Am I right? But I don't know how difficult is then implementation on the PC side.

 

I will check this XAPP anyway.

 

Thanks

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