Full logic simple SPI read

[Dermiste]

Morning Xilinx community,

I've been a developper for 10 years and I'm getting started with FPGA on a new project: 40+ SPI slave in parallel for large sensor acquisition. In order to achieve that I will start simple and try to read one sensor's UID using only logic, no soft/hard processor. My hardware is a Spartan7 dev board.

I found the examples for QuadSPI & Axi Traffic Generator and I have the following questions:

• in the QuadSPI example, 3 ATG write in turns data and then check their values, to which memory do they write? I cannot find a specific bloc, only BRAM reference in the VHDL code.
• can I just connect the SPI FLASH of my Spartan7 to my QuadSPI output and expect my commands to go through without any setup for that particular memory?
• is there an IP that can act as a virtual SPI device (a simple memory?) which I can setup using a file ? That would help me focus on the write/read operation without having to care about a routine to init that memory.
• I've been using COE files to setup addresses and data and everytime I update their content, I need to wrap my design in HDL & synthesize it and finally startup the simulation again in order to visualize the changes, even that does not work every time and the whole process takes up about 5min. What is the correct way to do that? i.e to update files and see straight away the new data in my simulation without having to compile anything.

I'm new to Vivado and FPGA world I'm trying to focus in specific bits, step by step, to avoid building a big mess I don't control.

Thanks in advance for any tip or help !

[andresb]

Hi Dermiste,

Which Spartan-7 Eval board are you using? SP701?

Can you describe what kind of sensors you're trying to communicate with. How do they connect to the board?

Thanks,
Andres

[Dermiste]

Hello Andres,

Yes it's the SP701. Sensor wise we use what we produce in-house, gyros and accelerometers.

Before even trying to plug one sensor I would love to establish an efficient development process that allows me to quickly simulate transactions without having to re-build/compile everything everytime I change a register in the traffic generator, this is the main blocking point so far.

Thanks in advance for any tip

[drjohnsmith]

I would suggest you split the task into a hardware system that talks to the SPI , and probably looks like a uart to a "processor" system,

Then you can update the software to change how your talking to the sensors without having to change the chip.

A micorblaze might be a good way to look at the CPU side ,
The AXI SPI controler might be a good candidate for the SPI UART

You are going to run into some hardware problems.

If your driving that number of SPI slaves at once, then thats an big load, you will need to look carefully at termination of data and clocks,

Second, if your driving that many SPI slaves, you will need that number of SPI chip selects, which the standard peripherals wont support,

Third, depends how you wire that number, depends how many MOSI and MISO signals you have at the FPGA , that could be a lot of data muxing driving you need to sort out.