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rgrossman
Adventurer
Adventurer
6,201 Views
Registered: ‎12-03-2015

GIC interrupt numbering incorrect when using zc706 board

Hi,

 

I have noticed a problem with GIC interrupt numbering when generating a Petalinux (v2015.2.1) project from an HDF. The HDF file was generated with Vivado (v2015.2.1) having selected the zc706 board. The design has an AXI UARTLlite implemented with the interrupt connected to IQR F2P port 0. The pl.dtsi entry generated by Petalinux shows the interrupt at 91 (59+32=91), not the expected 61 (29+32=61).  I have corrected the interrupt number with an entry in system-top.dts.  When I implement the same design on a Zedboard the interrupt is correctly numbered as 61. The rest of the pl.dtsi entry for the axi_uartlite is the same.

 

From zc706 pl.dtsi:

    interrupt-parent = <&intc>;

    interrupts = <0 59 1>;
    port-number = <1>;

 

From Zedboard pl.dtsi:

    interrupt-parent = <&intc>;
    interrupts = <0 29 1>;
    port-number = <1>;

 

 

This numbering problem is consistent for all PL interrupts. I am now trying to add an axi_iic device and the interrupt is also incorrect and it seems to be interferirng with the axi_uartlite implementation.  I am unable to receive the uartlite interrupts with the axi_iic in the design.

 

Are there know problems with the zc706 board files?  

Are there any updated files (contraints, etc) for the zc706?  

Has anyone else seen these problems?

 

Thanks,

Ron

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liup1990
Observer
Observer
921 Views
Registered: ‎06-14-2018

Hi,

     have you sovled this problem?I meet the problem too.

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