GPIO PIN MAPPING

[pmaurice]

I have created a block design with a custom board based on zynqMP.

I am trying to use AXI4 GPIO IP and i don't understand how to map the gpio pin.

I have connected everything , validated design and everything "seems" fine but when i launch the synthesis and I open the synthesized design and go in layout i/o port and I don't see the axi4 gpio IP in there.

what i am suppose to do in order to map the AXI4 GPIO somewhere....???

I know it is probably a waste of time because all my forums questions/issues never been resolve here and I ended up to click accept as solution to prevent spam on my e-mail.

[miker]

@pmaurice

Can you elaborate on your use-case?

Q1:  Are you trying to utilize the Processing System (PS) GPIO via EMIO through the Programmable Logic (PL)?  (I assume no)
Q2:  Are you trying to utilize the AXI GPIO LogiCORE (PG144) in the PL?  (I assume yes)
Q2a:  If yes, are you trying to control the AXI GPIO LogiCORE from the PS or from logic in the PL?

[pmaurice]

I have a zynqMP block in vivado and i connect axi4 gpio block on it with the GPIO output mark as external.

I try to map the GPIO pin somewhere on the zynq but can't find where/how since it doesnt appeir in the i/o ports layout after synthesis

[pmaurice]

 

 

[pmaurice]

I don't understand Q2a

[miker]

@pmaurice 

Did you expand your "Scalar Ports" listing to see if the GPIO were under that listing?

[pmaurice]

yes and they are not there either.

[miker]

@pmaurice 

I created a simple design utilizing the AXI GPIO LogiCORE memory mapped to the Zynq UltraScale+ MPSoC PS.

I configured the AXI GPIO LogiCORE as an 8-bit output.

I performed the following steps:

1. Created a Block Design and added the Zynq UltraScale+ MPSoC and the AXI GPIO IPs to the canvas.
2. Double-clicked on the AXI GPIO block and configured as 8 bit output and selected OK.
3. I selected the Run Connection Automation, selected All Automation, and selected OK.
4. Validated Block Design.
5. Right-clicked on the block diagram in the Sources window and selected Create HDL Wrapper... and selected Let Vivado manage wrapper and auto-update.
6. Generate Block Design.
7. Run Synthesis and opened synthesized design checkpoint.
8. Viewed the I/O Ports tab and found the GPIO.

I was able to map the GPIO to pins post-synthesis.  I have included an XDC with the project and commented out a possible port mapping for the GPIO.

I have attached the Vivado 2020.2 Project Archive example design.

[pmaurice]

I was able to map the GPIO to pins post-synthesis ======> HOW?

[pmaurice]

GPIO need to be connected on FPD or LPD ?

[miker]

@pmaurice 

I included my example design so you could reference locally.  I also provided the steps in case you had to recreate on an earlier version of Vivado.  I was able to view the GPIO ports post-synthesis in the I/O Ports view.

You did not provide your full design so there is no telling if there is optimization happening where resources are being trimmed and therefore the I/Os are not available.  My example design can at least provide you a flow to verify.

[pmaurice]

I have a custom board, I will drop the design that i got from manufacturer.

you will need to source scripts/create_project.tcl with vivado tcl to create the project.

plain project contain ddr4 and GPIO and when i run synthesis I can't see GPIO in the i/o ports.

[miker]

@pmaurice 

GPIO in the Programmable Logic (PL) via the AXI GPIO LogiCORE are powered by VCCO of their particular PL I/O Bank and not dependent on Low Power Domain (LPD) or Full Power Domain (FPD).  The LPD and FPD are specific to the Processing System (PS).

[miker · Accepted solution]

@pmaurice 

The only GPIO port from the Block Diagram that gets port mapped is gpio(1) and it is only used as a control signal to drive Led2_N (either '0' or value of LedCount(23)).

	MercuryXU9_i: component MercuryXU9
	   port map (
		gpio_tri_o(7 downto 0)			=> Gpio(7 downto 0),
		pl_clk1							=> Clk,
		pl_resetn0						=> Rst_N,
		DDR4_act_n						=> DDR4PL_ACT_n,
		DDR4_adr(16 downto 0)			=> DDR4PL_A(16 downto 0),
--		DDR4_adr(17 downto 0)			=> DDR4PL_A(17 downto 0),
		DDR4_ba(1 downto 0)				=> DDR4PL_BA(1 downto 0),
		DDR4_bg(0)						=> DDR4PL_BG(0),
--		DDR4_bg(1 downto 0)				=> DDR4PL_BG(1 downto 0),
		DDR4_ck_c(0)					=> DDR4PL_CK_N(0),
		DDR4_ck_t(0)					=> DDR4PL_CK_P(0),
		DDR4_cke(0)						=> DDR4PL_CKE(0),
		DDR4_cs_n(0)					=> DDR4PL_CS_n(0),
		DDR4_dm_n(7 downto 0)			=> DDR4PL_DM(7 downto 0),
		DDR4_dq(63 downto 0)			=> DDR4PL_DQ(63 downto 0),
		DDR4_dqs_c(7 downto 0)			=> DDR4PL_DQS_N(7 downto 0),
		DDR4_dqs_t(7 downto 0)			=> DDR4PL_DQS_P(7 downto 0),
		DDR4_odt(0)						=> DDR4PL_ODT(0),
		DDR4_reset_n					=> DDR4PL_RST_n,
		SYS_CLK_clk_n					=> CLK100_N,
		SYS_CLK_clk_p					=> CLK100_P
	  );

	Led2_N <= '0' when gpio(1) = '1' else LedCount(23);

entity system_top is
  port (
  
...
	---------------------------------------------------------------------------------------------------
	-- HP bank 64 (1.2 V)
	---------------------------------------------------------------------------------------------------
	
	I2c_Scl								: inout	std_logic;
	I2c_Sda								: inout	std_logic;
	
	Led2_N								: out	std_logic;

...
	);
end system_top;

Here is the post-synthesis schematic that makes it more clear:

If you want the AXI GPIO to drive a Programmable Logic (PL) IO, you will need to port map these GPIO signals to top-level IOs in your top-level VHDL file.

[pmaurice]

I don't understand.

[miker]

@pmaurice 

The AXI GPIO Ports that exit the block diagram do NOT get connected to top level ports in the VHDL Wrapper file which is why they are not visible in post-synthesis as I/O.  Only 1 of the 8 GPIO Ports gets connected as a signal and is actually used as a signal inside the FPGA (...not connected to an top level port).

[pmaurice]

@miker 

What is the fix I can do to make it work??

I really don't understand the subtilty here.

I have compiled the design you sent me and the gpio do get mapped , I don't understand the difference between the 2 design.

[pmaurice]

I am software engineer and English as second language.

I don't get to use vivado often, I have design IP blocks in Vitis HLS and i have devolpped code in vitis "sdk".

I basically only configure and connect blocks so far in vivado. I have never did vhdl/verilog and i don't even know where to go to access those.

The design i sent you is provided by the company to who we bought the board , is the design OK? (probably not since gpio don't work)

[miker]

@pmaurice 

The design provided by the board provider is implemented as advertised according to the PDF.  Their block diagram shows only driving a single LED (Led2_N).

You can modify their provided example design by mapping the GPIO ports from the instantiated block diagram to the top-level VHDL ports.  You would also need to update the constraints file to define which package pin the ports are mapped to and to define their IO standard.  With all that said, you really need to have someone whom is familiar with FPGA design assist you on this.

[pmaurice]

@miker 

Honestly, we are a small enterprise and I am at my own.

I am learning this from scratch. (so far I have used BRAM, DMA and FFT xilinx block ip module and on hls i did few custom IP to do DMA myself and stream processing ; Now i need to use few gpio blocks)

I took a look on what VHDL code looks like and i took a look too on the system_top_PE1.vhd and I start to understand what you mean by top level.

At what I saw , led2_N is define on top level. (This signal is in the I/O ports menu and is mapped.)

then, there is mercuryxu9 component define gpio_tri_o.

I will need to look further on this, but at the end there is a kind of script that is executed (mercuryxu9_i) which seems to map GPIO (external signal on block diagram) on the gpio_tri_o from mercury component. After that , there is a small script that is executed to make blink the led on the board according to a clock rising edge.

I think company tried to make abstraction with the baseboard and the chip on socket.

is system_top.vhd is automatically created or edited by vivado ?? In the project you gave me , the code is in Verilog instead of VHDL.

when you said "You would also need to update the constraints file to define which package pin the ports are mapped to and to define their IO standard. " are you talking about modifying the system_top.vhd ??

[miker]

@pmaurice 

From your description, it sounds like you are on the right path.

Q1:  Is system_top.vhd automatically created or edited by Vivado?
A1:  It can be either.  However, it looks like Mercury chose to manage the top level VHDL file (system_top_PE1.vhd) instead of having Vivado automatically generate and modify.

Q2:  When you said "You would also need to update the constraints file to define which package pin the ports are mapped to and to define their IO standard. " are you talking about modifying the system_top.vhd?
A2:  No, you would want to add it to the MercuryXU9_PE1.xdc constraint file.

Good luck.

[pmaurice]

@miker 

thanks for your patience.

I will go study VHDL so I can do the code modification.

Is there a way to directly contact you if I have further questions ?

[Rmccarty]

I think what you are missing is that you need output ports in the top level diagram that are also listed in the configuration file (.xdc). This will connect the signal to the pin listed in the xdc. My board came with a filled-out and commented xdc, all i had to do was uncomment the port pins i wanted to use and change the names to correspond to my block diagram.