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Anonymous
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Generating a 1.92 MHz clock using the CLKOUT4_CASCADE atribute of the MMCM

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Hi,

 

We're trying to generate a 1.92 MHz clock by dividing a 15.36 MHz clock signal. The target device is a Zynq xc7z045-2ffg900 (speed grade -2) AP SoC.

 

In the 7 Series FPGAs Clocking ResourcesUser Guide it is said that it should be possible by enabling CLKOUT4_CASCADE. Nevertheless, there is no example on how to do it.

 

We have been trying to play with different CLKFBOUT_MULT_F and DIVCLK_DIVIDE options (also combined with the CLKOUT0_DIVIDE_F value). None of the values that are providing an output clock of 1.92 MHz seems to be valid when implementing the design (i.e., it is issued an error indicating that the FVCO is out of range).

On the other hand, it seems impossible to obtain a FVCO >=600 MHz without forcing a CLKOUT0_DIVIDE_F value higher than 128, which is indicated as out of range and, hence, the MMCM is not even generated (through the Clocking Wizard).

 

What are we doing wrong? Or better: how do we need to configure the MMCM in order to provide the required clock by using the CLK4OUT_CASCADE option?

 

Thank you very much in advance!

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Anonymous
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I don't know if that's of interest to anyone, but I'm providing a solution that seems to work (at least the system can be implemented and the behavioral simulation is as expected.
In short, when CLK4OUT_CASCADE is enabled, the frequency of CLK4OUT is provided by:
 - (CLKIN1_FREQUENCY*(CLKFBOUT_MULT_F/DIVCLK_DIVIDE))/(CLKOUT4_DIVIDE*CLKOUT6_DIVIDE)

That is, the value of CLKOUT4_DIVIDE can be extended beyond 128 by using CLKOUT6_DIVIDE. Then, with an input clock of 15.36 MHz, we can use the following values:

- CLKFBOUT_MULT_F = 64
- DIVCLK_DIVIDE = 1
(the previous two values provide a FVCO of 983.04 MHz, which is within the required range for the zynq device).
- CLKOUT4_DIVIDE = 128
- CLKOUT6_DIVIDE = 4
(providing an absolute division value of 512, resulting in CLK4OUT@1.92 MHz).

Here you have the VHDL code:

MMCME2_ADV_inst : MMCME2_ADV GENERIC MAP (
    BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED")
    CLKFBOUT_MULT_F => 64.0, -- Multiply value for all CLKOUT (2.000-64.000).
    CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (0.00-360.00).
    -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    CLKIN1_PERIOD => 65.104,
    CLKIN2_PERIOD => 0.0,
    -- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
    CLKOUT1_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT2_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT3_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT4_DIVIDE => 128, -- Results in an output clock@1.92 MHz
    CLKOUT5_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT6_DIVIDE => 4,     -- Results in an output clock@245.76 MHz
    CLKOUT0_DIVIDE_F => 128.0, -- Divide amount for CLKOUT0 (1.000-128.000).
    -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
    CLKOUT0_DUTY_CYCLE => 0.5,
    CLKOUT1_DUTY_CYCLE => 0.5,
    CLKOUT2_DUTY_CYCLE => 0.5,
    CLKOUT3_DUTY_CYCLE => 0.5,
    CLKOUT4_DUTY_CYCLE => 0.5,
    CLKOUT5_DUTY_CYCLE => 0.5,
    CLKOUT6_DUTY_CYCLE => 0.5,
    -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
    CLKOUT0_PHASE => 0.0,
    CLKOUT1_PHASE => 0.0,
    CLKOUT2_PHASE => 0.0,
    CLKOUT3_PHASE => 0.0,
    CLKOUT4_PHASE => 0.0,
    CLKOUT5_PHASE => 0.0,
    CLKOUT6_PHASE => 0.0,
    CLKOUT4_CASCADE => TRUE, -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
    COMPENSATION => "ZHOLD", -- "ZHOLD", "INTERNAL", "EXTERNAL" or "BUF_IN"
    DIVCLK_DIVIDE => 1, -- Master division value (1-106)
    -- REF_JITTER: Reference input jitter in UI (0.000-0.999).
    REF_JITTER1 => 0.0,
    REF_JITTER2 => 0.0,
    STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (TRUE/FALSE)
    -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
    CLKFBOUT_USE_FINE_PS => FALSE,
    CLKOUT0_USE_FINE_PS => FALSE,
    CLKOUT1_USE_FINE_PS => FALSE,
    CLKOUT2_USE_FINE_PS => FALSE,
    CLKOUT3_USE_FINE_PS => FALSE,
    CLKOUT4_USE_FINE_PS => FALSE,
    CLKOUT5_USE_FINE_PS => FALSE,
    CLKOUT6_USE_FINE_PS => FALSE
  )
  PORT MAP (
    -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0 output
    CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0 output
    CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1 output
    CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1 output
    CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2 output
    CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2 output
    CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3 output
    CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3 output
    CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4 output
    CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5 output
    CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6 output
    -- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
    DO => OPEN, -- 16-bit output: DRP data output
    DRDY => OPEN, -- 1-bit output: DRP ready output
    -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
    PSDONE => OPEN, -- 1-bit output: Phase shift done output
    -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock output
    CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
    -- Status Ports: 1-bit (each) output: MMCM status ports
    CLKFBSTOPPED => OPEN, -- 1-bit output: Feedback clock stopped output
    CLKINSTOPPED => OPEN, -- 1-bit output: Input clock stopped output
    LOCKED => LOCKED, -- 1-bit output: LOCK output
    -- Clock Inputs: 1-bit (each) input: Clock inputs
    CLKIN1 => clk, -- 1-bit input: Primary clock input
    CLKIN2 => clk, -- 1-bit input: Secondary clock input
    -- Control Ports: 1-bit (each) input: MMCM control ports
    CLKINSEL => '1', -- 1-bit input: Clock select input
    PWRDWN => '0', -- 1-bit input: Power-down input
    RST => RST, -- 1-bit input: Reset input
    -- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
    DADDR => "0000000", -- 7-bit input: DRP adrress input
    DCLK => clk, -- 1-bit input: DRP clock input
    DEN => '0', -- 1-bit input: DRP enable input
    DI => "0000000000000000", -- 16-bit input: DRP data input
    DWE => '0', -- 1-bit input: DRP write enable input
    -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
    PSCLK => clk, -- 1-bit input: Phase shift clock input
    PSEN => '0', -- 1-bit input: Phase shift enable input
    PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
    -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock input
  );
  -- End of MMCME2_ADV_inst instantiation
 
  -- BUFG: Global Clock Buffer
  -- 7 Series
  -- Xilinx HDL Libraries Guide, version 13.1
  BUFG_inst : BUFG
  PORT MAP (
    O => CLKFBIN, -- 1-bit output: Clock buffer output
    I => CLKFBOUT -- 1-bit input: Clock buffer input
  );
  -- End of BUFG_inst instantiation

Cheers,
Oriol

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Highlighted
Scholar
Scholar
7,027 Views
Registered: ‎11-09-2013

the best way would be:

 

1 use 15.36 clock internally and only use Clock enable at 1.92mhz rate

2 if used extenall generate the 1.92mhz directly in IO flip flop

 

my 2 cents

 

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Anonymous
Not applicable
7,024 Views

Thank you for your answer trenz-al.

 

We already thought of using a clock-enable signal, but it is not the most convenient solution for our design (i.e., it would require a major redesign and the system uses other clocks, which would complicate the generation of a reliable control-plane).

 

Some tips on how to use the CLK4OUT_CASCADE feature?

 

Thanks!

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Xilinx Employee
Xilinx Employee
7,015 Views
Registered: ‎02-06-2013

Hi

 

You can use a counter to divide the frequency by 8 to generate 1.92MHZ clock from your input clock.

Regards,

Satish

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Anonymous
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Hi Satish,

 

thank you for your answer. I'm assuming that you imply to generate a clock-enable signal with the counter. In such case, it is not a convenient solution for us (please, see the answer that I prevously provided above yours).

 

Best regards,

Oriol

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Xilinx Employee
Xilinx Employee
7,003 Views
Registered: ‎02-06-2013

 

Hi

 

You cannot generate 1.92Mhz from the MMCM even by using the cascade feature as the VCO frequency will not be met and also it is

 

outside the possible range that can be generated by the MMCM.

 

Have a look at the MMCM_FOUTMIN Value in the below doc

http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

Regards,

Satish

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Anonymous
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Hi again,

 

in the document that you linked (we had already seen it) it is stated that "When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz", which is clearly below the targeted 1.92 MHz frequency.

 

Regarding the FVCO, I do agree that it needs to be mantained at least to 600 MHz. Going back to the 7-series clocking user guide, it is also stated that when CLKOUT4_CASCADE is enabled "Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384".

 

Hence, if we do understand it correctly, in theory we could mantain a combination of CLKFBOUT_MULT_F and DIVCLK_DIVIDE values, which given the input clock, would result in a FVCO of at least 600 MHz. Then we would need to use a CLKOUT0_DIVIDE_F value greater than 128 (or a value of 128 and do something else, allowing the previously mentioned division up to 16384). The problem is that nowhere it is specified how to do that (i.e., how to cascade the output divider [counter] of CLKOUT6 to obtain this greater division).

 

Thanks again,

Oriol

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Anonymous
Not applicable
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I don't know if that's of interest to anyone, but I'm providing a solution that seems to work (at least the system can be implemented and the behavioral simulation is as expected.
In short, when CLK4OUT_CASCADE is enabled, the frequency of CLK4OUT is provided by:
 - (CLKIN1_FREQUENCY*(CLKFBOUT_MULT_F/DIVCLK_DIVIDE))/(CLKOUT4_DIVIDE*CLKOUT6_DIVIDE)

That is, the value of CLKOUT4_DIVIDE can be extended beyond 128 by using CLKOUT6_DIVIDE. Then, with an input clock of 15.36 MHz, we can use the following values:

- CLKFBOUT_MULT_F = 64
- DIVCLK_DIVIDE = 1
(the previous two values provide a FVCO of 983.04 MHz, which is within the required range for the zynq device).
- CLKOUT4_DIVIDE = 128
- CLKOUT6_DIVIDE = 4
(providing an absolute division value of 512, resulting in CLK4OUT@1.92 MHz).

Here you have the VHDL code:

MMCME2_ADV_inst : MMCME2_ADV GENERIC MAP (
    BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED")
    CLKFBOUT_MULT_F => 64.0, -- Multiply value for all CLKOUT (2.000-64.000).
    CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (0.00-360.00).
    -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    CLKIN1_PERIOD => 65.104,
    CLKIN2_PERIOD => 0.0,
    -- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
    CLKOUT1_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT2_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT3_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT4_DIVIDE => 128, -- Results in an output clock@1.92 MHz
    CLKOUT5_DIVIDE => 128, -- Results in an output clock@7.68 MHz
    CLKOUT6_DIVIDE => 4,     -- Results in an output clock@245.76 MHz
    CLKOUT0_DIVIDE_F => 128.0, -- Divide amount for CLKOUT0 (1.000-128.000).
    -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
    CLKOUT0_DUTY_CYCLE => 0.5,
    CLKOUT1_DUTY_CYCLE => 0.5,
    CLKOUT2_DUTY_CYCLE => 0.5,
    CLKOUT3_DUTY_CYCLE => 0.5,
    CLKOUT4_DUTY_CYCLE => 0.5,
    CLKOUT5_DUTY_CYCLE => 0.5,
    CLKOUT6_DUTY_CYCLE => 0.5,
    -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
    CLKOUT0_PHASE => 0.0,
    CLKOUT1_PHASE => 0.0,
    CLKOUT2_PHASE => 0.0,
    CLKOUT3_PHASE => 0.0,
    CLKOUT4_PHASE => 0.0,
    CLKOUT5_PHASE => 0.0,
    CLKOUT6_PHASE => 0.0,
    CLKOUT4_CASCADE => TRUE, -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
    COMPENSATION => "ZHOLD", -- "ZHOLD", "INTERNAL", "EXTERNAL" or "BUF_IN"
    DIVCLK_DIVIDE => 1, -- Master division value (1-106)
    -- REF_JITTER: Reference input jitter in UI (0.000-0.999).
    REF_JITTER1 => 0.0,
    REF_JITTER2 => 0.0,
    STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (TRUE/FALSE)
    -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
    CLKFBOUT_USE_FINE_PS => FALSE,
    CLKOUT0_USE_FINE_PS => FALSE,
    CLKOUT1_USE_FINE_PS => FALSE,
    CLKOUT2_USE_FINE_PS => FALSE,
    CLKOUT3_USE_FINE_PS => FALSE,
    CLKOUT4_USE_FINE_PS => FALSE,
    CLKOUT5_USE_FINE_PS => FALSE,
    CLKOUT6_USE_FINE_PS => FALSE
  )
  PORT MAP (
    -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0 output
    CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0 output
    CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1 output
    CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1 output
    CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2 output
    CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2 output
    CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3 output
    CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3 output
    CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4 output
    CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5 output
    CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6 output
    -- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
    DO => OPEN, -- 16-bit output: DRP data output
    DRDY => OPEN, -- 1-bit output: DRP ready output
    -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
    PSDONE => OPEN, -- 1-bit output: Phase shift done output
    -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock output
    CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
    -- Status Ports: 1-bit (each) output: MMCM status ports
    CLKFBSTOPPED => OPEN, -- 1-bit output: Feedback clock stopped output
    CLKINSTOPPED => OPEN, -- 1-bit output: Input clock stopped output
    LOCKED => LOCKED, -- 1-bit output: LOCK output
    -- Clock Inputs: 1-bit (each) input: Clock inputs
    CLKIN1 => clk, -- 1-bit input: Primary clock input
    CLKIN2 => clk, -- 1-bit input: Secondary clock input
    -- Control Ports: 1-bit (each) input: MMCM control ports
    CLKINSEL => '1', -- 1-bit input: Clock select input
    PWRDWN => '0', -- 1-bit input: Power-down input
    RST => RST, -- 1-bit input: Reset input
    -- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
    DADDR => "0000000", -- 7-bit input: DRP adrress input
    DCLK => clk, -- 1-bit input: DRP clock input
    DEN => '0', -- 1-bit input: DRP enable input
    DI => "0000000000000000", -- 16-bit input: DRP data input
    DWE => '0', -- 1-bit input: DRP write enable input
    -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
    PSCLK => clk, -- 1-bit input: Phase shift clock input
    PSEN => '0', -- 1-bit input: Phase shift enable input
    PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
    -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock input
  );
  -- End of MMCME2_ADV_inst instantiation
 
  -- BUFG: Global Clock Buffer
  -- 7 Series
  -- Xilinx HDL Libraries Guide, version 13.1
  BUFG_inst : BUFG
  PORT MAP (
    O => CLKFBIN, -- 1-bit output: Clock buffer output
    I => CLKFBOUT -- 1-bit input: Clock buffer input
  );
  -- End of BUFG_inst instantiation

Cheers,
Oriol

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Visitor
Visitor
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Registered: ‎03-28-2016

I need a larger divide because I have a slow 2.5 MHz input clock, so I make "CLKOUT4_CASCADE = True" and I'm using the output of CLKOUT4 as the feedback, so I know the phase of the output of CLKOUT4 is the same as the input clock because of the phase comparator. What is the phase of the output of the other CLKOUTx since I need a multiplied version of the input clock with a known phase (a VERY common configuration)?

 

UG472 says, "There is a static phase offset between the output of the cascaded divider and all other output dividers." What is that "static" phase shift? Does it vary with temperature? Do CLKOUT4_PHASE and the other CLKOUTx_PHASE operate as expected or is there some unknown phase shift?

 

P.S. HOW DO I START A NEW THREAD?!

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Observer
Observer
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Registered: ‎09-03-2017

Please share the generation of 2.5 MHz CLOCK IN artix FPGA board by MMCM

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