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serdarrpf
Visitor
Visitor
10,328 Views
Registered: ‎06-15-2015

Generating clock with vivado

Hi,

I am using Vivado with a ZedBoard  programming in VHDL (PL). The ZedBoard clock source for PL is 100Mhz. I need two clocks: clkgen1= 100kHz and clkgen2= 350Mhz to clock the FMC.

 

How can I generate these clocks in Vivado? I know I can use PLL or Mmcm. Which one would be better?

 

Is there any tutorial?

 

Thank you.

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balkris
Xilinx Employee
Xilinx Employee
10,315 Views
Registered: ‎08-01-2008

---- Where can i read documentation about this?

You can find documents about zed board in the following board’s link http://www.xilinx.com/support/university/boards-portfolio/xup-boards/XUPZedBoard.html .

-------How can i do this in Vivado?
Check whether the below thread applicable to your issue
http://forums.xilinx.com/xlnx/board/crawl_message?board.id=GenDis&message.id=18987

________________________________________________
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
10,314 Views
Registered: ‎08-01-2008

related discussion

http://forums.xilinx.com/t5/Design-Entry/Configuration-of-PLL-ZedBoard/m-p/598773#M8485
Thanks and Regards
Balkrishan
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aher
Xilinx Employee
Xilinx Employee
10,300 Views
Registered: ‎07-21-2014

Hi,
You can find more information regarding 7 series clocking resources (MMCM/PLL) in following UG.

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

PLL is actually a subset of MMCM. General usage description of these resources, you can find at page 67 of this user guide.

Thanks,
Shreyas
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serdarrpf
Visitor
Visitor
10,298 Views
Registered: ‎06-15-2015

The thread is about

ZedBoard Vivado licence??

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smarell
Community Manager
Community Manager
10,269 Views
Registered: ‎07-23-2012

Where is the PL clock coming from? Why are you not considering to use FCLK available in PS?

If the clock is coming to the PL then you can use either MMCM or PLL. Please note that PLL is a subset of MMCM functionalities.

I would recommend you to refer to UG482 and PG065.
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