02-09-2021 09:43 AM - edited 02-09-2021 10:35 AM
Big picture. Two related DMA codes, one is S2MM and the other is MM2S. They do not run at the same time. In both cases, I'm following the ideas expressed in SG interrupt example code except that they have been separated to execute at different times. I've augmented the code to count interrupt executions.
The S2MM code (S is an ADC) is SG (scatter/gather) code that captures data to 8Kbyte buffers (i.e. each BD points to an 8K block). I've set the IRQThreshold to 1 and the IRQDelay to zero.
In this S2MM case, I successfully get about one interrupt per BD.
In the MM2S case, I'm doing the same thing but I get only one interrupt. I am using 32K buffers in this case. The S is in this case is not a DAC exactly, but DAC captures the idea. I.e., I'm playing the data to something like a DAC.
However, I get only one interrupt. As before I've set the IRQThreshold to 1 and the IRQDelay to zero.
Is there anything I'm missing?
Unfortunately, I cannot easily set up a project that looks like the example. Also, the code in the example wants to have only one interrupt so I can't know that what I'm doing actually works, though what I've read in these pages indicates they should work the same.
¿Is there any relationship between IOC interrupts and the TLAST signal?
The poor quality of these examples is a real burn of my time. Can we hope that with the purchase things will improve?
02-09-2021 11:33 AM
Go to your IPI / Block diagram, double click on the AXI Direct Memory Access IP to customize it, and check the field labeled "Width of Buffer Length Register". Is it still 14? Change it to 15 if this turns out to be your problem.
02-09-2021 12:35 PM
Thanks, @maps-mpls. No that is not the problem. The Xilinx code returns an error the code exceeds the length of the register.
The H/W guy is telling me that the is no TLAST and I'm wondering if that is the problem.
As I said I successfully transfer all of the data, but I only get one interrupt -- at the end of the chain, which is marked as such.