12-09-2016 11:13 PM
I am working on zynq7020 customized board, I am working on CCD CAMERA Module, I have created the complete video pipeline part in PL side . now I have to give this to my customer , my customer need to add some more logic into PL Side, But I cant directly give my PL Design to them. when I am searching someone posted about the NETLIST, from that they extract the design and add their logic into PL side. could u please explain WHAT and HOW can I generate my complete PL DESIGN NETLIST.
12-10-2016 02:54 AM
Sounds like what you actually need is an encrypted IP core, so you can hand them the complete core but they won't be able to access the code that generated it. Have a look in UG896 for details on this.
12-10-2016 04:18 AM
thanks for the reply , ya it is some think like encrypted but I want to encrypt my full project not a single IP core, in ug896 that is not given. and with that encrypted project customer has to add their logic. please help me
12-10-2016 12:12 PM
@theertharamesha what you need is to define a module which includes all your IP so that only its input/output is visible at the top level and then encrypt the whole thing so that your customer can instantiate your IP, their own logic and connect them properly. You can define a top level IP which includes all your pipeline. IP doesn't mean a single/small block, the whole pipeline can be an IP block too.
12-14-2016 09:57 PM
Hi, thanks for the reply . I have created the IP of my complete project . but I don't know how to encrypt that IP CORE. I have referred the Xilinx ip core creation document also but there they have not explained anything about IP ENCRYPTION. can u please tell how can I encrypt my IP CORE or tell me which document I should refer.
12-15-2016 08:05 AM