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theertharamesha
Adventurer
Adventurer
3,813 Views
Registered: ‎08-21-2016

HOW TO GENERATE COMPLETE PL SIDE NETLIST

hi,

 

I am working on zynq7020 customized board, I am working on CCD CAMERA Module, I have created the complete video pipeline part in PL side . now I have to give this to my customer , my customer need to add some more logic into PL Side, But I cant directly give my PL Design to them. when I am searching someone posted about the NETLIST, from that they extract the design and  add their logic into PL side. could u please explain WHAT and HOW can I generate my complete PL DESIGN NETLIST.

 

WITH REGARDS

RAMESH

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6 Replies
u4223374
Advisor
Advisor
3,796 Views
Registered: ‎04-26-2015

Sounds like what you actually need is an encrypted IP core, so you can hand them the complete core but they won't be able to access the code that generated it. Have a look in UG896 for details on this.

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theertharamesha
Adventurer
Adventurer
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Registered: ‎08-21-2016

thanks for the reply , ya it is some think like encrypted but I want to encrypt my full project  not a single IP core, in ug896 that is not given. and with that encrypted project customer has to add their logic. please help me

 

 

with regards

ramesh

 

 

 

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muzaffer
Teacher
Teacher
3,765 Views
Registered: ‎03-31-2012

@theertharamesha what you need is to define a module which includes all your IP so that only its input/output is visible at the top level and then encrypt the whole thing so that your customer can instantiate your IP, their own logic and connect them properly. You can define a top level IP which includes all your pipeline. IP doesn't mean a single/small block, the whole pipeline can be an IP block too. 

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theertharamesha
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Adventurer
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Registered: ‎08-21-2016

Hi, thanks for the reply . I have created the IP of my complete project . but I  don't know how to encrypt that IP CORE. I have referred the Xilinx ip core creation  document also but there they have not explained anything about IP ENCRYPTION. can u please tell how can I encrypt my IP CORE or tell me which document I should refer.

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muzaffer
Teacher
Teacher
3,681 Views
Registered: ‎03-31-2012

@theertharamesha Xilinx support ieee-1735 encryption and it has a tool to do this but you need a license to use it: https://www.xilinx.com/support/answers/68071.html

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theertharamesha
Adventurer
Adventurer
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Registered: ‎08-21-2016

hi muzafer,

is there any other way to do the encryption?


how can I get my design netlist?



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