06-28-2021 05:37 AM
I'm trying to benchmark the speed of the HP FPD interface of a TE0802 board featuring a xczu2cg-sbva484-1-e SOC.
To do so i wrote an AXI master that will flood the interface with operations, as fast as the AXI backpressure signals allow.
This code has aready been vaildated on a 7 series ZYNQ.
It looks like that there is a problem the on the PS site, since one time every two writings the RLAST signal is not issued.
According to the AXI4 specification, the slave MUST drive RLAST on the last transaction beat.
Is there any other signal to look at tho debug this issue?
06-30-2021 07:48 PM
Here are a couple things to look at & for:
Just some quick thoughts. I don't see the problem as of yet, but perhaps those ideas will help you focus your search a bit.
07-01-2021 03:06 AM
1) I posted a screenshot with this values too, the red signal is generated with a counter that will calculates where the RLAST signal il supposed to be (delayed by one clock cycle)
2) I don't get you, ARSIZE is 0x7, and it's just the per beat data width (128 bits), the burst size is expressed in beats, I'm allowed to read at any address I want except for the 4K bounday limit, beside that my addresses are always aligned to ARSIZE.
3) It seem to be correct... I never set anything different from 128.
Thanks for your help!!!