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marcoventurini
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Registered: ‎10-02-2014

HP FPD inteface non issuing RLAST signal

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Hello,

I'm trying to benchmark the speed of the HP FPD interface of a TE0802 board featuring a xczu2cg-sbva484-1-e SOC.

To do so i wrote an AXI master that will flood the interface with operations, as fast as the AXI backpressure signals allow.

This code has aready been vaildated on a 7 series ZYNQ.

2021-06-28_12-48.png

It looks like that there is a problem the on the PS site, since one time every two writings the RLAST signal is not issued.

According to the AXI4 specification, the slave MUST drive RLAST on the last transaction beat.

marcoventurini_0-1624883678325.png

Is there any other signal to look at tho debug this issue?

Thanks,

 

Marco

 

 

 

 

 

 

 

 

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dgisselq
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Registered: ‎05-21-2015

@marcoventurini ,

The correct ARSIZE for a per beat data width of 128 is 3'h4, not 3'h7.  See if that makes a difference.

Dan

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marcoventurini
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Registered: ‎10-02-2014

An additional information, the Master is directly connected to the PS logic, there is no interconnect in between,

 

2021-06-28_15-13.png

 

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dgisselq
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Registered: ‎05-21-2015

@marcoventurini ,

Here are a couple things to look at & for:

  • Check out the ARID and RID values.  If the burst being returned is changing mid burst, it might look like you get two bursts worth of information at a time.
  • Your ARADDR isn't consistent with a burst size of anything other than ARSIZE=3'h0.  I'd be curious to know if this is the burst size you are using
  • There have been struggles with other users interacting with the ARM processor where the ARM is configured for the wrong bus size.  Therefore, I'd recommend you check out the bus size to see if it is properly configured or not.  If it is misconfigured, I'm told rebuilding the boot loader will fix it.

Just some quick thoughts.  I don't see the problem as of yet, but perhaps those ideas will help you focus your search a bit.

Dan

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marcoventurini
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Registered: ‎10-02-2014

Thanks @dgisselq,

1) I posted a screenshot with this values too, the red signal is generated with a counter that will calculates where the RLAST signal il supposed to be (delayed by one clock cycle)

2) I don't get you, ARSIZE is 0x7, and it's just the per beat data width (128 bits), the burst size is expressed in beats, I'm allowed to read at any address I want except for the 4K bounday limit, beside that my addresses are always aligned to ARSIZE.

3) It seem to be correct... I never set anything different from 128.

Thanks for your help!!!

 

marcoventurini_0-1625133825042.png

 

marcoventurini_1-1625133928622.png

 

 

 

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dgisselq
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Registered: ‎05-21-2015

@marcoventurini ,

The correct ARSIZE for a per beat data width of 128 is 3'h4, not 3'h7.  See if that makes a difference.

Dan

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marcoventurini
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Registered: ‎10-02-2014

Hello Dan

... my bad! I read bits instead of bytes... I will try right now.

Thanks!

 

Thanks,

 

Marco

marcoventurini_0-1625142607542.png

 

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marcoventurini
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Registered: ‎10-02-2014

I confirm that the problem was the incorrect ARSIZE.

Thanks

 

Marco

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