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Visitor
Visitor
255 Views
Registered: ‎09-09-2019

Hard/Soft reset results sometimes into loss of connection on AMM Master Bridge

My question is regarding answer record

https://www.xilinx.com/support/answers/72484.html

According to this issue is being resolved in 2019 but in 2020 i still see the same issue. have a look at the block diagram

problem_path.jpg

So what we have observed that upon power up or on soft reset we have issues . Issue is we have external master connected to internal memory through above defined path and sometimes on power up or on soft reset from zynq that external master(connected through AMM master bridge) get stalled because AMM master bridge doesn't respond.

Upon further investigation we have seen that external master which is getting signals from AMM bridge doesnt get the read request acknowledge. 

I had previously contacted xilinx regarding this issue and they told me that will be solved in 2019 but even now 2020 issue is still there. Any idea or work around to solve this issue

 

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Scholar
Scholar
238 Views
Registered: ‎05-21-2015

@mumar,

Consider adding an AXI firewall to your design--something that will be able to timeout and return a bus error on any failure to return an acknowledgement.

Dan

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Visitor
Visitor
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Registered: ‎09-09-2019

Problem is in AMM bridge, if I put AXI firewall after the bridge I need to write another bridge that will convert axi signals to external/Avalon like signals., putting between amm and interconnect doesn't do any good.

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