cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
alibarghi
Visitor
Visitor
6,402 Views
Registered: ‎06-08-2014

High current draw by zynq Z020 after Programming

Hi

I've assembled an Zynq (Z020) board; It detected by IMPACT but after  Program Zynq, it sink more current from  1 V (power Supply). 
Where is the problem? please help me. 

 

My Code:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TEST is
    Port (
           LED : out  STD_LOGIC
         );
end TEST;

architecture Behavioral of TEST is

begin

LED <= '1' ;
--LED <= '0' ; It is tested and has same problem

end Behavioral;

 And My Schematic is attached:

Only XILINX
0 Kudos
13 Replies
austin
Scholar
Scholar
6,386 Views
Registered: ‎02-27-2008

a,

 

"More current"?  Is the current expected (estimated by power estimator, or predicted by power analyzer)?

 

"More" is unhelpful.  A number is useful.

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
alibarghi
Visitor
Visitor
6,367 Views
Registered: ‎06-08-2014


@austin wrote:

a,

 

"More current"?  Is the current expected (estimated by power estimator, or predicted by power analyzer)?

 

"More" is unhelpful.  A number is useful.


Hi 

Thank your replies.

about 2 Amps at 1 volt and Other voltages typical current draw.

In addition, the program works correctly, but the problem is the high current.

 

Only XILINX
0 Kudos
alibarghi
Visitor
Visitor
6,365 Views
Registered: ‎06-08-2014

I test this program on zedboard and IC temperature was normal but my board had too high temperature. I do this over and over again, but I'm still having problems.
please help me.
Only XILINX
0 Kudos
austin
Scholar
Scholar
6,351 Views
Registered: ‎02-27-2008

2 amps is a reasonable number (depends on how it is configured),


What do the tools predict?

 

Perhaps you need a heatsink/fan?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
trenz-al
Scholar
Scholar
6,346 Views
Registered: ‎11-09-2013

Austin

 

see his code, it is one output.

 

device is 7020

 

2A is NOT reasonable at all.

 

7045 would take almost 2.5 IDLE current at high temperature, but 7020 is different matter

 

 

 

0 Kudos
austin
Scholar
Scholar
6,343 Views
Registered: ‎02-27-2008

t,

 

What if he instantiated a few thousand ring oscillators in the programmable logic?  It is prett easy to create designs that sink a lot of current.  I have no idea what this poster is actually doing.  Many times someone makes a "small change" not realizing what they have done.


Right now I am working with Ken Chapman's xapp555 design.  In that he has 1,000 PicoBlaze power consuming "cores" which can be used to generate many amperes of core current.  At some point, one may overwhelm the pcb power distribution, and the part droops below the startup threshold, cleans out, and needs to be configured.

 

"Lots" "too much" "high" are all relative.  In this case, relative to what?  To the as shipped design, unmodified?  How is the design modified?  What software, and what programmable logic is now added?  What did the tools predict the power would be?  How does the prediction compare with what is measured?  How is it measured?  How accurate?  What is the junction temperature of the device?

 

It is basic engineering:  do the work, get the answers.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
trenz-al
Scholar
Scholar
6,336 Views
Registered: ‎11-09-2013

Austin

 

OP wote in VHDL in his postings:

 

LED <= '1' ;

 

If this design takes 2A from 1V in 7020 at any temperature then something IS WRONG.

 

Any FPGA can be made to explode sure :) but not with one static output driving high level.

 

0 Kudos
austin
Scholar
Scholar
6,327 Views
Registered: ‎02-27-2008

t,

 

I agree.

 

 If ALL he does is turn one ONE LED and gets 2.0A, runs it again turning OFF ONE LED, and gets a nominal value (say 1 ampere), then something is defintely wrong.

 

At that point, I suggest he looks at the two designs, and discovers exactly what the difference is.

 

Somehow I do not believe that in the SAME design, turning on the led takes 2A, and turning it off takes 1 ampere (read a switch, turn it on, or off).

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
trenz-al
Scholar
Scholar
6,325 Views
Registered: ‎11-09-2013

Read again :)

 

he tried OFF and ON

 

both cases did take 2A

0 Kudos
austin
Scholar
Scholar
3,059 Views
Registered: ‎02-27-2008

ok,

 

Has he tried another bitstream?  (perhaps the original image shipped with the board)

 

If it now draws 2A (even unconfigured), then the device is damaged (most probably from ESD).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
trenz-al
Scholar
Scholar
3,053 Views
Registered: ‎11-09-2013

he is trying OWN board, so he has no factory golden image.

 

ESD damage is rahter rare, and I would expect dead not responding chip, not FPGA that starts consuming too much vccint after configuration.

0 Kudos
austin
Scholar
Scholar
3,051 Views
Registered: ‎02-27-2008

t,

 

ESD has been rare, in the past.  But with dimensions now at 28nm, and 20nm, even though the parts meet their stated ESD immunity levels (see ug116), the margin is just not there.

 

I would encourage everyone who is using this latest technology to take a refresher course in ESD control.  Use wrist straps, grounded equipment and benches, proper handling materials (anti-static, etc.).  The days of safely ignoring ESD control are over now.

 

No loose papers on the bench, no styrofoam cups, ...

 

Evaluation boards have practically no protection at all:  interfaces to the device are just waiting to get zapped (if one is ignoring ESD control).

 

When designed into products, and complying with UL, FCC, TuV, etc. the devices are then well protected.  Any device that blows out from a static charge in a product, also will not meet the other requirements (think of ESD as 'just 6 GHz RF -- if it leaks out, it will also leak in).

 

I want people to create new products with their boards.  I do not want unhappy people with broken boards.

 

Caveat Confrero

 

(Beware collection -- of electrons!  What is the latin word for static electricity???)

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
wellcores_shu
Visitor
Visitor
1,700 Views
Registered: ‎02-09-2015

My question on this is:

In ug933, it's said " PS_DDR_VREF0/1 should be left floating when DDR is not used or if the internal VREF is in use."

and " PS_DDR_VREF0 and PS_DDR_VREF1 provide a voltage reference for the PS_DDR_DQ and
PS_DDR_DQS input receivers".

But in his case, it's only 1 DDR chip used, if not all DQS useful, e.g. 32bit DQ use 4 DQS and 1 x16 DDR chip may use only 2 DQS, in this single DDR case, is that one PS_DDR_VREF should be left floating if relevent DQS is not connected?

 

Thanks

shu

0 Kudos