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gdg
Explorer
Explorer
5,027 Views
Registered: ‎03-22-2017

High-performance coherent vs. non-coherent (AXI ports)

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Which are the pros and cons of using AXI HPC (high-performance coherent) w.r.t. HP (non-coherent) interfaces? Which interface is faster?

 

In the software, are cache flush and invalidation necessary only for the non-coherent interfaces? For example:

 

 

	// Flush the cache
// **** Is this necessary only for non-coherent interfaces? *** Xil_DCacheFlushRange((INTPTR) input_data_stream, IMG_SIZE * sizeof(u32)); Xil_DCacheFlushRange((INTPTR) output_data_stream, IMG_SIZE * sizeof(u32));
XFilter_3x3_impulse_strm_Set_height_V(&Filter_3x3_impulse_strm, IMG_NROWS); XFilter_3x3_impulse_strm_Set_width_V(&Filter_3x3_impulse_strm, IMG_NCOLS); XFilter_3x3_impulse_strm_Start(&Filter_3x3_impulse_strm); // Data from the DMA (DRAM) to IP core XAxiDma_SimpleTransfer(&axiDMA, (INTPTR) input_data_stream, IMG_SIZE * sizeof(u32), XAXIDMA_DMA_TO_DEVICE); // Data from the IP core to the DMA (DRAM) status = XAxiDma_SimpleTransfer(&axiDMA, (INTPTR) output_data_stream, IMG_SIZE * sizeof(u32), XAXIDMA_DEVICE_TO_DMA); while (XAxiDma_Busy(&axiDMA, XAXIDMA_DMA_TO_DEVICE)) { /* Wait */ } while (XAxiDma_Busy(&axiDMA, XAXIDMA_DEVICE_TO_DMA)) { /* Wait */ } // Invalidate the cache to avoid reading garbage
// **** Is this necessary only for non coherent interfaces? **** Xil_DCacheInvalidateRange((INTPTR) output_data_stream, IMG_SIZE * sizeof(u32));
while (!XFilter_3x3_impulse_strm_IsDone(&Filter_3x3_impulse_strm));

 

 

HP_interfaces.png

1 Solution

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florentw
Moderator
Moderator
7,038 Views
Registered: ‎11-09-2015

Hi @gdg,

 

Which are the pros and cons of using AXI HPC (high-performance coherent) w.r.t. HP (non-coherent) interfaces?

-> Refer to the TRM (UG1085) table 35-4

trm.JPG

I would add the variable PL data bus width support (32/64/128) for HP.

 

Which interface is faster?

-> The HP because it does not need to go through the CCI-400

 

In the software, are cache flush and invalidation necessary only for the non-coherent interfaces?

-> For most of the systems yes. But you can have non-coherent transaction through HPC interfaces. But assuming you will keep AxCACHE[3:2] to any non-zero value then you won't need to flush or invalidate the cache.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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3 Replies
florentw
Moderator
Moderator
7,039 Views
Registered: ‎11-09-2015

Hi @gdg,

 

Which are the pros and cons of using AXI HPC (high-performance coherent) w.r.t. HP (non-coherent) interfaces?

-> Refer to the TRM (UG1085) table 35-4

trm.JPG

I would add the variable PL data bus width support (32/64/128) for HP.

 

Which interface is faster?

-> The HP because it does not need to go through the CCI-400

 

In the software, are cache flush and invalidation necessary only for the non-coherent interfaces?

-> For most of the systems yes. But you can have non-coherent transaction through HPC interfaces. But assuming you will keep AxCACHE[3:2] to any non-zero value then you won't need to flush or invalidate the cache.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

muzaffer
Teacher
Teacher
4,961 Views
Registered: ‎03-31-2012

@florentw

 

>> Which interface is faster?

>> -> The HP because it does not need to go through the CCI-400

 

Do HP ports have higher throughput or just better latency ? Can you quantify what "faster" means here?

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florentw
Moderator
Moderator
4,955 Views
Registered: ‎11-09-2015

Hi @muzaffer,

 

You are right, "faster" is a bit too general. It is only less latency.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**