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dinaemadeldin
Observer
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Registered: ‎07-15-2020

How can I define AXI4 full data size to be larger than 32 bit?

When I generate an AXI4 Full IP the only one available choice for data width which is 32 bit but according to the documents the AXI4 full can support up to 1024 bits, can I simply modify it in the code or I should use the default

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@dinaemadeldin,

I'd recommend trying to match the master's width to the slave's width.  Doing otherwise would be an exercise in futility--costing more resources, and taking longer to complete an operation than necessary.  Beyond that, you are more than welcome to edit the .xml and .tcl files to adjust your design if necessary.  I've had to do so more than once with some of my custom IPs when Vivado couldn't handle the changes I needed.

Dan