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wsipak
Contributor
Contributor
714 Views
Registered: ‎03-05-2019

How can I know why Vivado sets specific clock frequencies?

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I'm using Zynq-7000.
I want to set PL clock FCLK_CLK0 to 100MHz.
As far as I know, in order to get 100MHz, I need to set these parameters:
Input frequency : 33.33 MHz
IOPLL Multiplier: 30 (to get IOPLL clock 1000MHz)
FCLK_CLK0 first divisor: 5, second divisor: 2 (to get 100MHz from 1000MHz).
That's what I do in Vivado, and it shows that Actual Frequency will be 100MHz.

However, when I generate bitstream Vivado changes the value and Actual Frequency becomes 102MHz.
I'm trying know the reason of this, but Vivado doesn't give much information. What I get is "Unable to generate the reuired set of clock frequencies [...] see the ps_clock_registers.log file [..]"
Unfortunately, this file is empty.

I attach screenshots which present:
1. Clock settings that are correct and should result in 100MHz on FCLK_CLK0.
2. Clock settings that appear after I run the whole pipeline to generate bitstream.

I know this is design-specific but what I need to know is where I can find
details about what happens there. Log outputs say nothing about the clock being
102MHZ.

Edit: I think I cannot add descriptions for each attachment, please take a look at filenames to know which are correct.

 

wrong.png
wrong2.png
correct.png
clocks_correct_before_implementation.png
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1 Solution

Accepted Solutions
sabankocal
Voyager
Voyager
691 Views
Registered: ‎08-02-2019

Hi @wsipak ,

I can recommend to you, without touching any advanced setting, simply changing PL Fabric Clocks-->FCLK_CLK0 to 100MHz, only doing that.

Because most of the reference designs uses 50MHz clock and 100MHz is very normal value to achieve.

To initialize all of yor settings to default, you can see screen shot.

 

Saban

 

<--- If reply is helpful, please feel free to give Kudos, and close if it answers your question --->

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Set_PL_Clock_To_100MHz.png
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2 Replies
sabankocal
Voyager
Voyager
692 Views
Registered: ‎08-02-2019

Hi @wsipak ,

I can recommend to you, without touching any advanced setting, simply changing PL Fabric Clocks-->FCLK_CLK0 to 100MHz, only doing that.

Because most of the reference designs uses 50MHz clock and 100MHz is very normal value to achieve.

To initialize all of yor settings to default, you can see screen shot.

 

Saban

 

<--- If reply is helpful, please feel free to give Kudos, and close if it answers your question --->

View solution in original post

Set_PL_Clock_To_100MHz.png
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wsipak
Contributor
Contributor
659 Views
Registered: ‎03-05-2019

Thank you for your reply.

Vivado wouldn't allow me to change anything of the clock settings because every time I would get the message:

Unable to generate the required set of clock frequencies [...] see the ps_clock_registers.log file

It seems like the problem disappeared when I recreated the Zynq component.

Unfortunately, The output clock I get is not exactly 100MHz, but it's another kind of problem.

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