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helmutforren
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How do I connect 3rd party master AXIS to Microblaze master AXI?

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I'm using Vivado 2018.1 and Block Diagram.

 

EDIT: Is my answer the axi_mm2s_mapper (AXI Memory Mapped to Stream Mapper IP)?  [EDIT: NO!]

 

In my block diagram, I have a 3rd party IP (aka "3pIP") that has one AXI-Stream input (slave S00_AXIS) and one AXI-Stream output (master M00_AXIS) .  They are used to write and read control registers.  I need to connect BOTH of them to my MicroBlaze, also in the block diagram.  I already have an AXI Interconnect in my block diagram, that routes the MicroBlaze M_AXI_DP to multiple slaves.  How do I add this 3pIP into the picture?

 

An answer from the above paragraph would be great.  Otherwise, I write a little further about what I see.  The MicroBlaze M_AXI_DP appears to be bi-directional.  It has both M_AXI_DP_RDATA[31:0] input and M_AXI_DP_WDATA[31:0] output.  Meanwhile the 3pIP ports are both uni-directional:  S00_AXIS has only S00_AXIS_tdata[31:0] input while the M00_AXIS has only M00_AXIS_tdata[31:0] output.  Meanwhile, the AXI Interconnect has multiple ???_AXI that are also bi-directional.

 

So it seems to me that I need to somehow MERGE the 3pIP's uni-directional S00_AXIS and M00_AXIS ports into a single bi-directional slave port.  Then I could connect it to yet one more master output of the AXI Interconnect. 

 

This is in contrast to the easier "visual" of connecting the 3pIP's slave to a new AXI interconnect master and the 3pIP's master to a new AXI interconnect slave.  I don't think this will work, because the AXI interconnect will NOT be able to connect the 3pIP's master to the MicroBlaze master.

 

 

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helmutforren
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tedbooth
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The MicroBlaze M_AXI_DP is an AXI-Lite interface.  It is typically used for reading and writing registers in IPs.  Ideally, your "3pIP" should have a slave AXI-Lite interface for accessing the control registers.  From there is would be a simple matter to connect the AXI-Lite interfaces via an AXI_Interconnect.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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helmutforren
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Thanks @tedbooth , but as I mentioned, the "3pIP" is THIRD PARTY.  I have no control over it and can't change it. 

 

Do you know if the AXI Memory Mapped to Stream Mapper IP (axi_mm2s_mapper) will do the job I need?  I was able to connect it up in the block diagram already.  I'm working on ouside-the-block-diagram connections right now, before I can test it.

https://www.xilinx.com/support/documentation/ip_documentation/axi_mm2s_mapper/v1_1/pg102-axi-mm2s-mapper.pdf

 

BTW, it is registers I'm writing and reading, but the third party IP has them on separate AXI-Stream ports, and then has a few operational AXI-Stream output ports with which I have no problem.

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tedbooth
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That being the case, I think the MM2S Mapper IP is probably your best bet.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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stephenm
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You can use the Tools -> Create or Import IP wizard to create your own custom IP with AXI interface

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helmutforren
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@stephenm , I'm aware of this.  But how do you suggest it helps in this specific case?  If the AXI Memory Mapped to Stream Mapper IP (axi_mm2s_mapper) might do the job, why would I create new IP to solve this problem?

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helmutforren
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