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SriramGangadhar
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Registered: ‎09-14-2020

How do I verify if my processor Clock is entering my custom IP?

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I am trying to do a simple Image processing application on Zedboard, where I have created a custom IP to perform Image blurring. (I have tested/simulated this IP and it works, i.e, Giving an image input activates all modules and I get the required output image). I created an AXI4-Stream interface as the top module and packaged this.

When i finished by block diagram to combine my PS and and PL using the AXI DMA controller, I do not get an output from this module. Using the Debug tool I have verified that my data enters the IP, but nothing leaves it.

Upon further testing and debugging interior signals in my IP, I found that my counters are not counting. From my understanding this could only be due to the PS clock not entering the system as my reset is not active (checked using the debugger). Is it possible to check the clock coming in from the PS using the debug tool and display it?

If my assumption is indeed right what could be the reason that my clock is not getting activated inside my module. Could there be any other reason for my codesign not work given that the IP works on its own, but fails when I integrate it in a block design.

 

Block Diagram, Img_blur is my custom IPBlock Diagram, Img_blur is my custom IPMy DMA controller transmits but receives nothing from the IP (checking both the s2mm interrupt and status register ). Any help in regard to this would help me a lot.

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dgisselq
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Registered: ‎05-21-2015

@SriramGangadhar,

Beware of the S2MM bug ... if data arrive at the S2MM controller before it has been programmed for data transfer, it will hang.

Beyond that, the easy way to check for the presence of a clock is to drive a 26-28 bit counter (depending on the clock speed) from that clock, and then send the MSB to an LED.  If the LED blinks, the clock is present.  If not, the clock is absent.  If you have two clocks, you can also count the ones speed using the other.

Dan

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dgisselq
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Registered: ‎05-21-2015

@SriramGangadhar,

Beware of the S2MM bug ... if data arrive at the S2MM controller before it has been programmed for data transfer, it will hang.

Beyond that, the easy way to check for the presence of a clock is to drive a 26-28 bit counter (depending on the clock speed) from that clock, and then send the MSB to an LED.  If the LED blinks, the clock is present.  If not, the clock is absent.  If you have two clocks, you can also count the ones speed using the other.

Dan

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SriramGangadhar
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Registered: ‎09-14-2020

@dgisselq 

Thanks for that. I verified that my clock is indeed running in my IP.

However my design still fails. As I mentioned, data enters my IP, but I do not get any output (M_AXIS Interface has no output signals). Simulating the IP on its own at the same clock frequency yields a proper output.

Is there any reason why this might be the case?

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dgisselq
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Registered: ‎05-21-2015

@SriramGangadhar,

Without any more knowledge than what you've given me, I'd guess:

  1. You haven't formally verified any of your logic
  2. You hit one of the bugs in Xilinx's demonstration cores (They didn't formally verify their cores either, and there are some nasty bugs within them.)
  3. You hit the bug in the S2MM core.

At this point and without any more information, I couldn't tell you which it is.

Dan

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bruce_karaffa
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Registered: ‎06-21-2017

It might be time to put some ILAs in your design to see why it isn't working.