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Contributor
Contributor
569 Views
Registered: ‎06-28-2019

How to Start off interfacing BRAM through ethernet (RJ45) in Xilinx vivado & SDK with Zynq Ultrascale+ ZCU102

Hi,

I want to connect the data in Block ram of Zync Ultrascale+ ZCU102 through ethernet RJ45. I would like to get reference links, tutorials regarding how to start about this in Xilinx Vivado and SDK. Details about this would help me go forward.

Thank you.

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Moderator
Moderator
511 Views
Registered: ‎07-31-2012

Hi @bharaini ,

 

XAPP1305 reference design has few examples with PS GEM (1G) to board RJ45 port use that design and instantiate BRAM to the design.

Else it has stream FIFO IP which can be used as well.

 

Regards

Praveen


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Contributor
Contributor
500 Views
Registered: ‎06-28-2019

Hi @pvenugo 

Thanks for the reply. I will surely look into the reference and get back to you.

Thank you.

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Contributor
Contributor
471 Views
Registered: ‎06-28-2019

Hi @pvenugo 

I just went through the reference that you had mentioned, there it is done using petalinux. Is there any other references/tutorial where in it could be done in Windows. Also provide me details on reference/tutorial links from where I can learn concepts related to this.

Thank you.

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Moderator
Moderator
454 Views
Registered: ‎07-31-2012

Hi @bharaini ,

In baremetal/Standalone OS  there is no ready available application but you may need to modify LWIP application (available in SDK) which used TCP/UDP stack to send packets.

Refer to https://www.xilinx.com/support/documentation/application_notes/xapp1306-ps-pl-ethernet-performance-lwip.pdf

Or, could used Ethernet IP's example C application from SDK and modify to execute.

Regards

Praveen

 


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Contributor
Contributor
445 Views
Registered: ‎06-28-2019

Hi @pvenugo 

Thanks for the reply. I will surely look into this reference that you have given. 

Also I got another reference link, here it is 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841889/Zynq-7000+AP+SoC+-+Performance+-+Ethernet+Packet+Inspection+-+Bare+Metal+-+Redirecting+Packets+to+PL+Tech+Tip

Can I use this to solve my problem statement.

Thank you.

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Contributor
Contributor
435 Views
Registered: ‎06-28-2019

Hi @pvenugo

As a part of the same question that I had posted, I started by running the Zynq Ultrascale+ MpSoc with the AXI BRAM Controller in Vivado. 

I have also launched the same in SDK through the LWIP echo server. Now how do I extract the data which is given in BRAM as coe file through the ethernet. How should I go about in analysing and making changes in the C code.

Thank you.

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