06-29-2019 02:28 AM
I want to connect the data in Block ram of Zync Ultrascale+ ZCU102 through ethernet RJ45. I would like to get reference links, tutorials regarding how to start about this in Xilinx Vivado and SDK. Details about this would help me go forward.
06-30-2019 09:23 AM
Hi @bharaini ,
XAPP1305 reference design has few examples with PS GEM (1G) to board RJ45 port use that design and instantiate BRAM to the design.
Else it has stream FIFO IP which can be used as well.
06-30-2019 10:12 AM
07-01-2019 02:04 AM
I just went through the reference that you had mentioned, there it is done using petalinux. Is there any other references/tutorial where in it could be done in Windows. Also provide me details on reference/tutorial links from where I can learn concepts related to this.
07-01-2019 09:42 PM
Hi @bharaini ,
In baremetal/Standalone OS there is no ready available application but you may need to modify LWIP application (available in SDK) which used TCP/UDP stack to send packets.
Or, could used Ethernet IP's example C application from SDK and modify to execute.
07-02-2019 12:26 AM
Thanks for the reply. I will surely look into this reference that you have given.
Also I got another reference link, here it is
Can I use this to solve my problem statement.
07-02-2019 04:50 AM
As a part of the same question that I had posted, I started by running the Zynq Ultrascale+ MpSoc with the AXI BRAM Controller in Vivado.
I have also launched the same in SDK through the LWIP echo server. Now how do I extract the data which is given in BRAM as coe file through the ethernet. How should I go about in analysing and making changes in the C code.