How to Use AXI4 for DDR3 RAM with Target Language being VHDL?
I want to use the AXI4 with DDR3 SDRAM on the vc707 dev board. I also plan to connect microblaze to this interconnect to initialize the RAM. A BRAM connection will also be made to read and write data in bursts to the DDR3 SDRAM.
Since I am new to IPs, I decided to use the MIG (version 2.3 rev. 1) with Vivado 2015.1. The problem is that with target language set to VHDL, I am not able to use AXI4. I do not want to use verilog and Vivado does not have an option for mixed projects.
What are my options here? How can I solve this issue without ending up to use verilog in the entire project?
you can always instantiate a verilog module into a vhdl block. So just generate the ip in verilog. It should give you the component declaration which you can use it to instantiate in your design. Luckily Vivado allows mixed-language designs.
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