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deepakb
Contributor
Contributor
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Registered: ‎08-07-2013

How to access PS DDR using two master interfaces at same time

Hello,

We are having 2 master IPs which are trying to access the PS DDR at a time. One master IP is having 3 master ports and connected to S_AXI_HP0_FPD bridge and other is having 4 master ports and connected to S_AXI_HP1_FPD bridge using AXI interconnect in both cases.

Is it possible to access both slave bridges at a time? In general how this case will be taken care? I feel like there will be some kind of address collision since both ,aster IPs may try to acceess same location since they are independent. Or is there any limitations like two masters cannot access the PS DDR at a time?

I hope the my query is clear.

Thanks and Regards,

DPK

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mattwaltz
Adventurer
Adventurer
442 Views
Registered: ‎06-05-2017

There's an internal interconnect in the PS that arbitrates access to the DDR controller. Refer to page 27 in the document below (UG1085):

 

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

 

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