06-02-2014 03:29 PM
My PL custom IP has a master AXI port that is generating low speed 32 bit words. This master AXI is connected via AXI interconnect to PS S_AXI_GP0. What is the standard method for accessing this data on the PS side? The Vivado Address Editor seems to only provide addresses from the PL (master) side.
06-03-2014 09:51 AM
I am unclear on the mechanism for accessing data received by a PS slave AXI. Data transmitted from a PS master AXI to a custom IP slave AXI is available in a register as defined in the auto generated S00_AXI.v file. Is there a similar register defined for the PS slave AXI? A DDR location could be fine as well. Do I need to write PS software to setup resources to save incoming data?
06-03-2014 12:05 PM