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Adventurer
Adventurer
3,688 Views
Registered: ‎01-22-2015

How to achieve High performance on zynq zc706 DDR3 SODIMM memory (PL)

Hi All,

 

Please look into the attached PDF of block design which I made for PL DDR3. I have four AXI masters in PL (only write) and one AXI read master from VDMA. I am using PL DDR3 SODIMM due to BW limitation on PS DDR. I need 3.84 Gbytes/sec including read and writes. I got around 960 Mbytes/sec when I am using the PS DDR(used HP ports), but after changing to PL SODIMM the performance is decreased. 

 

I have doubts on my PL DDR3 implementation, configuration. All AXI read and write data width is 64-bit. Please help me understand and achieve more performance on PL DDR3 (than PS DDR).

 

 

Thanks, 

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Xilinx Employee
Xilinx Employee
3,572 Views
Registered: ‎07-30-2007

A few quick tips:

  • Make sure that all masters SUPPORTS_NARROW_BURST = 0
  • Make sure that the crossbar width is the same as the MIG in interconnect_2
  • Make sure that nearly all accesses to MIG are at least 4 or maybe 8 beats long at the MIG AXI interface. AXI MIG is extremely inefficient at small burst lengths.
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