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Visitor
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Registered: ‎05-13-2009

How to add own IP (memory controller) to a MicroBlaze project

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Does anyone be able to explain some fundamental things related on
subject how to add own IP to a MB project. In my case I have found a complete
VHDL source for a memory controller and want to use that in my
application. I have to connect PLB bus signals to the IP. The

procedure I will use is following:

1) I use Create or Import Peripheral Wizard in the XPS
   I name my IP and input the selections wizard request

2) I notice that the wizard has created directory my_ip_v1_00_a.
   In that direcory there are sub directories
   \data,  \ devl, and \hdl. I included my ip by selecting my ip
   from IP catalog\Project Local pcores.

3) I modify the files (according instructions I found)
  
   myip_v2_1_0.mpd   (in directory \data)
  
   myip_app.vhd      (in directory \hdl\vhdl)
   user_logic.vhd    (in directory \hdl\vhdl)

   Principally I have added the user ports my application uses.


   I also edited .ucf file located in directory myproject\. This file has I/O pin
   definitions.

4) I locate file including my own ip, myip.vhd, to the same directory \hdl\vhdl

5) I modify the user_logic.vhd in order that it references my own ip. I also include
   the vhdl description which handles the transactions between PLB bus signals and signals
   used in my ip.

There is actually quite much work all that mentioned above. But I made an error somewhere.

An error message indicating that my ip block cannot be resolved, this can be caused by
misspelled type name, or missing edif or ngc file.

I wonder did I put myip.vhd to the right directory ? Or should I have compiled first my ip using
Xilinx ISE in order to produce .edif or .ngc file for my ip ?

Should my ip file myip.vhd be listed on the project files window ? The list where .mhs, .mss, .ucf
etc. are listed ?

Does anyone has a good example on how to add own ip to a MicroBlaze project. Such an example
which uses both write and read actions of PLB bus ? I have studied the Xilinx example project "
Lab 3: Adding Custom IP to an Embedded System Lab" (University program material). Unfortunately
this example is too simple, having only write action. And the IP included in that example is bit

too simple.
  
Xilinx documents which handles these issues Processor IP Reference Guide  (Feb.2005) or

User Core Templates Reference Guide (Aug.2003) are missing practical examples.

 

 

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Explorer
Explorer
14,399 Views
Registered: ‎05-15-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello,

The trick is to look at this task from the simplest way possible, so you can understand it. So, here it goes,

 

The microblaze processor architecture possesses a bus denoted PLB (Processor Local Bus). Every IP core attached to the PLB has two layers, necessary to provide interface from user logic (the vhd code responsible for the core functioning) to the PLB signals, which are the IPIF (IP Interface to PLB interface) and IPIC (IP Interconnect to provide interface between user logic and IPIF). The bottom line with the cores, namely in this case, the custom IP cores, is that you only need to concern with the user logic, usually user_logic.vhd placed in your core folder, if created it with the peripheral wizard. Pay attention to whatever connections you need to do with the IPIC signals, which you can easily see declared in the user_logic.vhd by default. This is your way to "talk" to the processor out of your core.

 

The user ports (if you have need for them) must be specified in user_logic and in the interface vhd (which normally is the other file in the same folder as the user_logic.vhd). More than declaring the user ports, you also have to make the propper connection, so that the signals are accessible to the outside of your core. For instance, I needed user ports to connect my core to a vhdl entity created in ISE.If your core is not connecting to anything outside themicroblaze architecture, you will not need to define user ports.

 

After you have made the necessary changes in the two .vhd files of the core, you have to use the wizard again, but this time to import the core. Choose the same name and same versionn (default), it will prompt you a message that the core already exists and you click OK and continue. After you have completed the wizard again to import the newly changed core, you have to add the core to the architecture by going through "IP Catalog", and selecting USER, and your core. Right-click it and then "Add IP". After this, you need to mark it to be attached to the PLB: from the system assembly view, bus interfaces, check the yellow little ball near your core name (click + on it so that you can chech the yellow ball). 

 

Then, go to "Ports", check that the connections to your core are well made, and click Addresses to associate an address space to your core so that you are able to interact from it via software (the C code you are running in BRAM, attached to the processor).

 

This will be it. the ucf will be created automatically, as well as the mhs and mss files. Messing with the ports in assembly view will change the mhs file.

 

If you need further help oin creating your custom core, feel free to ask.

 

Best,

JM

 

 

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Contributor
Contributor
12,125 Views
Registered: ‎05-25-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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You have to add myip.vhd to my_ip_v1_00_a\data\myip_v2_1_0.pao before the user_logic.vhd

 

For example:

(...cut, cut...)

lib my_ip_v1_00_a myip vhdl                #Your memory controller

lib my_ip_v1_00_a user_logic vhdl          #
lib my_ip_v1_00_a myip_app vhd            #Top level of the PLB IP

 

 

 

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Explorer
Explorer
14,400 Views
Registered: ‎05-15-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello,

The trick is to look at this task from the simplest way possible, so you can understand it. So, here it goes,

 

The microblaze processor architecture possesses a bus denoted PLB (Processor Local Bus). Every IP core attached to the PLB has two layers, necessary to provide interface from user logic (the vhd code responsible for the core functioning) to the PLB signals, which are the IPIF (IP Interface to PLB interface) and IPIC (IP Interconnect to provide interface between user logic and IPIF). The bottom line with the cores, namely in this case, the custom IP cores, is that you only need to concern with the user logic, usually user_logic.vhd placed in your core folder, if created it with the peripheral wizard. Pay attention to whatever connections you need to do with the IPIC signals, which you can easily see declared in the user_logic.vhd by default. This is your way to "talk" to the processor out of your core.

 

The user ports (if you have need for them) must be specified in user_logic and in the interface vhd (which normally is the other file in the same folder as the user_logic.vhd). More than declaring the user ports, you also have to make the propper connection, so that the signals are accessible to the outside of your core. For instance, I needed user ports to connect my core to a vhdl entity created in ISE.If your core is not connecting to anything outside themicroblaze architecture, you will not need to define user ports.

 

After you have made the necessary changes in the two .vhd files of the core, you have to use the wizard again, but this time to import the core. Choose the same name and same versionn (default), it will prompt you a message that the core already exists and you click OK and continue. After you have completed the wizard again to import the newly changed core, you have to add the core to the architecture by going through "IP Catalog", and selecting USER, and your core. Right-click it and then "Add IP". After this, you need to mark it to be attached to the PLB: from the system assembly view, bus interfaces, check the yellow little ball near your core name (click + on it so that you can chech the yellow ball). 

 

Then, go to "Ports", check that the connections to your core are well made, and click Addresses to associate an address space to your core so that you are able to interact from it via software (the C code you are running in BRAM, attached to the processor).

 

This will be it. the ucf will be created automatically, as well as the mhs and mss files. Messing with the ports in assembly view will change the mhs file.

 

If you need further help oin creating your custom core, feel free to ask.

 

Best,

JM

 

 

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Visitor
Visitor
12,109 Views
Registered: ‎05-13-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Thanks, these instructions might help me to right direction. But still something wonders me. I go through once again the Create and Import

Peripheral. And as you pointed out this time I import existing IP with the previous name and version and accept the overwritten.

Then I follow the wizard. But what then. You wrote that from IP catalog I should choose the the ip in section USER. I only 

can see section Project Local pcores where my ip is listed. If I now import the ip everything looks the same as before ? (I use 

Platform Studio version 9.2.) 

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Explorer
Explorer
12,095 Views
Registered: ‎05-15-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello,

I use EDK 10.1, there might be some slight changes. However, the important point is that you should Add your IP from the IP catalog to the microblaze architecture.

 

After you do the "overwrite" thingy on the wizard, you must follow the steps. Tick hdl sources, Add the *.pao file (search in data folder of your pcore, its there), attach to the PLB, etc etc, just follow the instructions of the wizard. 

 

Best,

JM 

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Participant
Participant
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Registered: ‎05-07-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello, JM

 

I am very glad to see your post about how to add a custom IP to microblaze.


The user ports (if you have need for them) must be specified in user_logic and in the interface vhd (which normally is the other file in the same folder as the user_logic.vhd). More than declaring the user ports, you also have to make the propper connection, so that the signals are accessible to the outside of your core. For instance, I needed user ports to connect my core to a vhdl entity created in ISE.If your core is not connecting to anything outside themicroblaze architecture, you will not need to define user ports.

 

I design a verlog module in ISE and I want the ports of this module to connect to my PowerPC440 module.

So, I am going to add a custom IP which can implement this connection to my PowerPC in XPS.

My design is like your example in your post. but there are something puzzled me.

 

1. Do I just add my ports in user_logic and in the interface vhd file and not care any ports of  IPIFand IPIC in these two vhd template files?

 

2. After I add this IP to my Powerpc, how can I access the data of my own ports and process these data in C application?  Whether there are some basic C functons to access my own ports?

 

I hope that you would give me more guidlines and help me to solve these  problems.

 

Thank you very much.

 

Best regards

 

AARON

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Explorer
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Registered: ‎05-15-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello aaron.

Glad I can help. As for your questions:

 

1) User ports are used to make external I/O connections to your core. Then, user_logic takes care of such signals and interacts with the PLB via the IPIF and IPIC layers. Therefore, you must code your user_logic treating the user signals as you like. For instance, if you want to generate an interrupt driven by an external signal you must say in your user_logic.vhd: "Ok, my external signal state is '1', then I must activate the interrupt using the right interface signal to the PLB, which will be IP2Bus_IntrEvent for this case".

 

2) hardware-software interface is made using registers, user core registers in your case. Your core must include registers (you can easily add this via the peripheral wizard). If you need help with this, just ask ;)

 

 

I will help you the best I know.

Best,

JM

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Participant
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Registered: ‎05-07-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello, JM

Thank you very much.

 

As you know, I will use my ports to make externel I/O connection. Among all of my ports, CLOCK port is more special than others.  My externel input CLOCK and PLB clk (Bus2IP_Clk) are two different clock domain. How can I process this cross clk domain?

 

For instance, my external input DATA is changed at the rising edge of my CLOCK. I want to deliver valid DATA through PLB and process DATA in my powerpc soft application. How can I deliver my DATA refering to My CLOCK and/or  PLB clk?

 

Looking forward to seeing your new post.

Thanks.

 

Best regards,

AARON

 

  

 

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Explorer
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Registered: ‎05-15-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello Aaron,

 

Your core *must* be synchronized with the PLB clock with an "if rising_edge(Bus2IP_Clk)" . You can then use your clock signal logic state (which i suppose it has lower frequency than the plb clk) to activate your desired core functionalities. Recall, however, to synch it with the plb clk with the if.

 

In your specific case, it's hard to guarantee that the rising edge of your clock falls within a plb rising edge. Mabe you should use only the logic state of the clock to trigger your data delivery. For example, within the if(rising_edge(Bus2IP_Clk), you can do a if (myClock = '1') and itnerrupt the cycle with a flag so that it only runs once when your clock is at a high state. then reset the flag when your clock is at the low state within the core. (This is just a 30 second idea, i'm shure you can figure out something more elegant). Data delivery may not fall at the exact rising edge time of your clock, however it should be really near. You can test this with an OSC to evaluate the delays.

 

Best,

JM

 

 

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Visitor
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Registered: ‎05-13-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hello,

 

thanks for help. I managed to locate my own vhd code in a separate file, locate the file in right directory, modify

the files including usr_logic.vhd. At least my application now manages to write to defined port address and probably

I could also read from some address if I have defined an input port. So I mark the problem solved sign.

 

But to go further in including a memory controller I need to access to bidirectional bus (data bus). So I need

input - output port. I believe I need to declare two signal names (or ports), one for output and one for input and

direct them to same port (defined in .mpd file) and physical pins (defined in .ucf file). 

Then I have to declare the port (register which I named in the wizard) to be type IO. But what else I need to make

it functioning ? Just naming the port to be IO (in .mpd file) I get an errors "TRI primitive obuft_0" has unconnected

ouput pin. I understod the tristate driving is missing. But where to find that ? Any signal in PLB bus ?Just needing

a bit idea of what is needed in birectional bus. The most simple realization.

 

Any help is wellcome. Thanks in advance.

 

best regards,

 

mikmaa

 

 

 

 

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Adventurer
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Registered: ‎06-05-2009

Re: How to add own IP (memory controller) to a MicroBlaze project

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Hi Mikmaa

According to the error message you showed, I think there may be the problem about the name of peripheral when you want to import the peripheral through Create and Import Pheripheral Wizard. Because it happened to me and showedthe same error message, bothering for a long while for me. 

 

When you want to import your peripheral through wizard, after you enter the name of the top VHDL entity, you have to tick the User Version, that should be the same name with the peripheral you created in ISE with the same User Version!!

 

Hope this will help you! After paying more attention to this point, I figure out this error and it work through.

 

Good Luck!

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