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Registered: ‎08-10-2009

How to add user defined external ports and make visible in ports tab of XPS

Hello ,

Good morning all

I want to add an counter logic to microblze.The counter will be reset from externel FPGA i/o pin and it will run with 200 MHZ clock  generated from PLL.

Now how can i add this user logic to microblaze using PLB .  I am attaching file user_counter.vhd for reference

can any body please explain how can i accomplish that ?


thanks in advance


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3 Replies
Registered: ‎08-29-2008



You need a user_counter.pao and user_counter.mpd file in addition and the following

user peripheral directory structure:







          |    |

          |    +-user_counter_v2_1_0.mpd

          |    +-user_counter_v2_1_0.pao






Examine an available example to lern more about the syntax of pao and mpd files ;-(




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Registered: ‎05-15-2009

I'm not sure if this is what you want, but here goes. 


From what i understood, you want to have a module attached to the microblaze PLB that implements a simple counter, however you need external pins to that module to make the reset from a pin attached to the expansion board of your FPGA ev board.


To accomplish this, you need to create a custom core. In XPS, use the Hardware -> Create or Import hardware to create a simple custom core. For help on this step, read  . It will create a folder under pcores/ with your choosen nam and inside, in vhdl/ folder, you will have the templates for user logic and the IPIF, in userlogic.vhd and mycorename.vhd. user_logic is where youb are going to implement your clock.


Then, you have to implement your counter in user logic., same code you use in your user_counter to implement it. Remember that it should run driven by the Bus2IP_Clk, which possesses the PLB clock frequency.


And about adding the external pins: You have to declare them in the specific portion of the user_logic code, which is normally under a specific section of the user_logic template for your core created by the peripheral wizard. Here's how to do.


1) In user logic, do


    -- ADD USER PORTS BELOW THIS LINE ------------------
    MY_EXTERNAL_PORT                                    : out std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------


 2) Make the port visible on the higher layer of the module


2.1)Open the yourcorename.vhd under pcores/yourcorename/vhdl/ and add the same as in user logic (search for this section under the template)


     -- ADD USER PORTS BELOW THIS LINE ------------------
    MY_EXTERNAL_PORT                                    : out std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------


2.2) Make the connections (search for this section under the template)


      -- MAP USER PORTS BELOW THIS LINE ------------------
         MY_EXTERNAL_PORT                                    =>  MY_EXTERNAL_PORT
      -- MAP USER PORTS ABOVE THIS LINE ------------------


2.3) Open again the Hardware -> Create/Import Peripheral and this time choose import peripheral. Follow the steps on the post i previously presented.



 3) After this, you will need to Project -> Rescan user repos. Now, go to the IP Catalog, under +User, right click on your core and "Add IP".


4) Under system assembly view-> Bus Interfaces, connect it  to the PLB byclicking on the yellow little ball


5) Under system assembly view ->Ports, open your core, and in the desired port named as MY_EXTERNAL_PORT choose make external.


6) Map its location on the UCF to the desired external pin under the data/ folder like this:




IMPORTANT NOTE: the name you use in the UCF is the name that is created when you select "make external" when assigning it external. Usually it goes by the name mycustomcorename_MY_EXTERNAL_PORT





Message Edited by jmonteiro-dme on 08-11-2009 04:13 AM
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Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007

Hi Sudhakar,


Chec kout XPs Timer/Counter,


If it doesn't server your purpose, it can still be used as an example to design your user counter peripheral.



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